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bogdan.deac
Contributor
Contributor
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Registered: ‎04-19-2017

SDSoC FPGA Resource Utilization

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Hello,

 

How can I obtain an FPGA used resources report from SDSoC (how many LUTs, FFs, etc. were used in total) ?

 

Best regards,

Bogdan D.

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kenkovaa
Contributor
Contributor
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Registered: ‎09-14-2017

Hi,

 

One way of analyzing the design is to open the design checkpoint and generate from there utilization reports in Vivado. To do that you can open the dcp in Vivado: "open_checkpoint C:/<workspace>/<appname>/Debug/_sds/p0/_vpl/ipi/imp/imp.runs/impl_1/zed_wrapper_routed.dcp" and then just switch to Default layout and issue "report_utilization -name foo" for example.

 

--Kim

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kenkovaa
Contributor
Contributor
1,100 Views
Registered: ‎09-14-2017

Hi,

 

One way of analyzing the design is to open the design checkpoint and generate from there utilization reports in Vivado. To do that you can open the dcp in Vivado: "open_checkpoint C:/<workspace>/<appname>/Debug/_sds/p0/_vpl/ipi/imp/imp.runs/impl_1/zed_wrapper_routed.dcp" and then just switch to Default layout and issue "report_utilization -name foo" for example.

 

--Kim

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tanders
Xilinx Employee
Xilinx Employee
979 Views
Registered: ‎03-31-2011

The Performance Estimate Report will give you a rough idea quickly.

The HLS Report, generated for each Hardware Function will give estimates per Function/Accelerator.

The vivado project: <project>/<config>/_sds/p0/vivado/prj/prj.xpr should give you complete view (e.g. utilization in the project summary), after a hardware build.

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