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meet.bais
Participant
Participant
743 Views
Registered: ‎10-22-2018

SDSoC platform generation

Hello.

i am doing the custom platform generation in the Vivado tool. After completing the exporting and  entire process of the platform generation  i am etting error while generating the DSA file for the same. Attaching files and screenshot of the same.

Capture.PNG

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6 Replies
nutang
Moderator
Moderator
692 Views
Registered: ‎08-20-2018

hi @meet.bais 

Attachments are missing.

Please upload them again.

Best Regards,
Nutan
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meet.bais
Participant
Participant
680 Views
Registered: ‎10-22-2018

@nutang 

i am unable to attach the project files.

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nutang
Moderator
Moderator
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Registered: ‎08-20-2018

Hi @meet.bais 

Is it possible to take the screenshot of error or just copy paste the error log here?

 

Best Regards,
Nutan
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meet.bais
Participant
Participant
653 Views
Registered: ‎10-22-2018

@nutang 

here is the error log

 

open_project C:/Users/Meet/Xilinx_projects/zybo7/zybo7.xpr
write_dsa -force ./zybo7.dsa
INFO: [Vivado 12-4895] Creating DSA: ./zybo7.dsa ...
CRITICAL WARNING: [Project 1-655] Project does not have Board Part set. Board related data may be missing or incomplete in the generated DSA.
WARNING: [Project 1-646] Board name, vendor and part not set in DSA.
WARNING: [Project 1-645] Board images not set in DSA.
CRITICAL WARNING: [Vivado 12-7009] BD 'zybo' is not in validated state. Please validate and re-generate the BD prior to generating a DSA. The BD can be validated in the GUI or by using Tcl command validate_bd_design in the Tcl console.
ERROR: [SDSoC-pfm-18] sdsoc::pfm_clock - clock domain 'zybo_processing_system7_0_0_FCLK_CLK0' for proc_sys_reset instance 'proc_sys_reset_0' does not match clock domain '/clk_wiz_0_clk_out1' for clock '/clk_wiz_0/clk_out1'
ERROR: [SDSoC-pfm-100] Incorrect 'clk_out1' value for the PFM.CLOCK of '/clk_wiz_0'
ERROR: [SDSoC-pfm-18] sdsoc::pfm_clock - clock domain 'zybo_processing_system7_0_0_FCLK_CLK0' for proc_sys_reset instance 'proc_sys_reset_1' does not match clock domain '/clk_wiz_0_clk_out1' for clock '/clk_wiz_0/clk_out2'
ERROR: [SDSoC-pfm-100] Incorrect 'clk_out2' value for the PFM.CLOCK of '/clk_wiz_0'
ERROR: [SDSoC-pfm-18] sdsoc::pfm_clock - clock domain 'zybo_processing_system7_0_0_FCLK_CLK0' for proc_sys_reset instance 'proc_sys_reset_2' does not match clock domain '/clk_wiz_0_clk_out1' for clock '/clk_wiz_0/clk_out3'
ERROR: [SDSoC-pfm-100] Incorrect 'clk_out3' value for the PFM.CLOCK of '/clk_wiz_0'
ERROR: [SDSoC-pfm-18] sdsoc::pfm_clock - clock domain 'zybo_processing_system7_0_0_FCLK_CLK0' for proc_sys_reset instance 'proc_sys_reset_3' does not match clock domain '/clk_wiz_0_clk_out1' for clock '/clk_wiz_0/clk_out4'
ERROR: [SDSoC-pfm-100] Incorrect 'clk_out4' value for the PFM.CLOCK of '/clk_wiz_0'
ERROR: [Vivado 12-5878] Failed to generate hpfm file for BD File: C:/Users/Meet/Xilinx_projects/zybo7/zybo7.srcs/sources_1/bd/zybo/zybo.bd
ERROR: [Common 17-53] User Exception: Unable to get hpfm file from project property dsa.hpfm_file or from the BD itself.
update_compile_order -fileset sources_1

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meet.bais
Participant
Participant
638 Views
Registered: ‎10-22-2018

@nutang 

Here is the error log

 

open_project C:/Users/Meet/Xilinx_projects/zybo7/zybo7.xpr
write_dsa -force ./zybo7.dsa
INFO: [Vivado 12-4895] Creating DSA: ./zybo7.dsa ...
CRITICAL WARNING: [Project 1-655] Project does not have Board Part set. Board related data may be missing or incomplete in the generated DSA.
WARNING: [Project 1-646] Board name, vendor and part not set in DSA.
WARNING: [Project 1-645] Board images not set in DSA.
CRITICAL WARNING: [Vivado 12-7009] BD 'zybo' is not in validated state. Please validate and re-generate the BD prior to generating a DSA. The BD can be validated in the GUI or by using Tcl command validate_bd_design in the Tcl console.
ERROR: [SDSoC-pfm-18] sdsoc::pfm_clock - clock domain 'zybo_processing_system7_0_0_FCLK_CLK0' for proc_sys_reset instance 'proc_sys_reset_0' does not match clock domain '/clk_wiz_0_clk_out1' for clock '/clk_wiz_0/clk_out1'
ERROR: [SDSoC-pfm-100] Incorrect 'clk_out1' value for the PFM.CLOCK of '/clk_wiz_0'
ERROR: [SDSoC-pfm-18] sdsoc::pfm_clock - clock domain 'zybo_processing_system7_0_0_FCLK_CLK0' for proc_sys_reset instance 'proc_sys_reset_1' does not match clock domain '/clk_wiz_0_clk_out1' for clock '/clk_wiz_0/clk_out2'
ERROR: [SDSoC-pfm-100] Incorrect 'clk_out2' value for the PFM.CLOCK of '/clk_wiz_0'
ERROR: [SDSoC-pfm-18] sdsoc::pfm_clock - clock domain 'zybo_processing_system7_0_0_FCLK_CLK0' for proc_sys_reset instance 'proc_sys_reset_2' does not match clock domain '/clk_wiz_0_clk_out1' for clock '/clk_wiz_0/clk_out3'
ERROR: [SDSoC-pfm-100] Incorrect 'clk_out3' value for the PFM.CLOCK of '/clk_wiz_0'
ERROR: [SDSoC-pfm-18] sdsoc::pfm_clock - clock domain 'zybo_processing_system7_0_0_FCLK_CLK0' for proc_sys_reset instance 'proc_sys_reset_3' does not match clock domain '/clk_wiz_0_clk_out1' for clock '/clk_wiz_0/clk_out4'
ERROR: [SDSoC-pfm-100] Incorrect 'clk_out4' value for the PFM.CLOCK of '/clk_wiz_0'
ERROR: [Vivado 12-5878] Failed to generate hpfm file for BD File: C:/Users/Meet/Xilinx_projects/zybo7/zybo7.srcs/sources_1/bd/zybo/zybo.bd
ERROR: [Common 17-53] User Exception: Unable to get hpfm file from project property dsa.hpfm_file or from the BD itself.
update_compile_order -fileset sources_1

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nutang
Moderator
Moderator
558 Views
Registered: ‎08-20-2018

Hi @meet.bais 

Looks like the BD is not valid.

Please validate and then generate bitstream

Best Regards,
Nutan
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