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Participant
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Registered: ‎11-16-2018

SDaccel 2018.2.xdf: Incorrect AXI4-lite Mapping in generated xclbin

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Hi!

I'm using SDAccel Manual flow (based on rtl_adder_pipes example).

In my case, I use 3 IPs connected using pipes, with each IP having an AXI4-lite interface

The synthesis runs smoothly (no ERROR or CRITICAL WARNING except the usual ones) but I can see that there is an issue in the generated xclbin file.

In the XML part, there is a description of each IP with their respective remapped addresses on the AXI4-lite bus.

Those addresses are empty for 2 of my IPs as shown in the attached screenshot.

However if I take a look a the file "_x/link/vivado/output/address_map.xml" the addresses are correctly inferred.

Moreover, if I test my design on Alveo U200 using the addresses from the "addres_map.xml" file it works perfectly.

Something wrong in the xclbin file generation?

Regards

 

 

 

 

 

SDx_2018.2.xdf_xclin_axi4l_addrremap_issue.png
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Participant
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Registered: ‎11-16-2018

Re: SDaccel 2018.2.xdf: Incorrect AXI4-lite Mapping in generated xclbin

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@kmorris ,

SDAccel 2019.1 failed at a very early stage pointing out the issue (kernel naming typo in xml file)

After fixing it, the xclbin file generated is now correct.

Regards

View solution in original post

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Xilinx Employee
Xilinx Employee
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Registered: ‎01-11-2011

Re: SDaccel 2018.2.xdf: Incorrect AXI4-lite Mapping in generated xclbin

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Hi @gdufourcq, would it be possible for you to test your design using 2018.3? There have been improvements in this area that hopefully corrects what you are seeing in the xclbin file.

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Participant
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Registered: ‎11-16-2018

Re: SDaccel 2018.2.xdf: Incorrect AXI4-lite Mapping in generated xclbin

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Hi,

I've just tested with 2018.3 and it shows the exact same issue

Regards

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Xilinx Employee
Xilinx Employee
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Registered: ‎01-11-2011

Re: SDaccel 2018.2.xdf: Incorrect AXI4-lite Mapping in generated xclbin

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Thank you for confirming that. Would you be able to send/attach your modified files from the rtl_adder_pipes example so we can replicate and examine the issue?

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Participant
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Registered: ‎11-16-2018

Re: SDaccel 2018.2.xdf: Incorrect AXI4-lite Mapping in generated xclbin

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Hi,

How can I share the project directly to you?

It contains sensitive data that I can't publish on such forum.

Regards

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Xilinx Employee
Xilinx Employee
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Registered: ‎01-11-2011

Re: SDaccel 2018.2.xdf: Incorrect AXI4-lite Mapping in generated xclbin

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I have sent you an EZMove email message from which you can upload the files directly to me. Let me know if you have any issues using it.

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Xilinx Employee
Xilinx Employee
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Registered: ‎01-11-2011

Re: SDaccel 2018.2.xdf: Incorrect AXI4-lite Mapping in generated xclbin

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Hi @gdufourcq, I have reviewed the files you provided and I do get the same results you reported. I do see that in your userip .xml files, there are no arguments defined within the <arg> tags. I wanted to clarify if it is intended for your userip to have no arguments?

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Registered: ‎11-16-2018

Re: SDaccel 2018.2.xdf: Incorrect AXI4-lite Mapping in generated xclbin

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Hi @kmorris,

Indeed my "user_ip" kernels have no arguments.

They are pure-RTL kernels that need only the pipe connection to the "drm" kernel.

FYI, I'm currently synthesizing on 2019.1 to see if the problem stills.

I'll keep you posted

Regards

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Participant
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Registered: ‎11-16-2018

Re: SDaccel 2018.2.xdf: Incorrect AXI4-lite Mapping in generated xclbin

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@kmorris ,

SDAccel 2019.1 failed at a very early stage pointing out the issue (kernel naming typo in xml file)

After fixing it, the xclbin file generated is now correct.

Regards

View solution in original post

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