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Adventurer
Adventurer
532 Views
Registered: ‎06-20-2019

Stream interface for kernel on Vitis

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Hello everyone,

 

I am trying to create an application project where my hardware function has a hls::stream type arguments. However, I am getting a weird error like:

'' kernel.xml indicates the existence of port OUTDATA, which does not exist"

"Error generating intermediate file /home/yahya/Desktop/vitis/..."

"Unable to create function map for HLS kernel"

This port exists and I think that it is because of the hls::stream typed argument. The reason of having this idea is that I have not seen any example project where hardware function has hls::stream argument. There is no example where "axis" is utilized as below. All examples have m_axi and s_axilite so is it a problem to use axis for hw function? If not, why would I have this issue?

#pragma HLS INTERFACE axis port=OUTDATA offset = slave bundle = gmem

 

Thank you for your time.

 

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Voyager
Voyager
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Registered: ‎10-21-2015

Hi

When you use SDSoC, have you created direct i/o(axis) interface for your sdsoc platform like this?

https://www.xilinx.com/html_docs/xilinx2019_1/sdsoc_doc/sdsoc-platform-examples-umx1504034375845.html?hl=axis

Similarly, you need to decalre axis port for your Vitis platform by refering to https://www.xilinx.com/html_docs/xilinx2019_2/vitis_doc/Chunk1756746358.html#phl1512685419302

Then connect an axis port of kernel  to the axis port interface of your platform

For that, refer to https://github.com/Xilinx/Vitis_Accel_Examples/tree/master/host/streaming_free_running_kernel/src

https://www.xilinx.com/html_docs/xilinx2019_2/vitis_doc/Chunk1180956723.html#itc1511211457306

 

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Moderator
Moderator
519 Views
Registered: ‎11-04-2010

If you intend to use stream ports between kernels, you can refer to:

https://github.com/Xilinx/SDAccel_Examples/blob/28322a4fa642cb9bc6302a14b481ce3b2cf5a447/getting_started/host/streaming_k2k_mm/src/krnl_stream_vmult.cpp

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Adventurer
Adventurer
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Registered: ‎06-20-2019
Thank you for your answer, I utilized the example and wrote some application accordingly. Yet, I am getting an error. Do you have any idea about the following error: No stream resources found that can accomodate compute unit "krnl_stream_1.input". What is the cause?
discussion: https://forums.xilinx.com/t5/Vitis-SDAccel-and-SDSoC/No-stream-resources-found-problem-on-Vitis-enviroment/m-p/1048842
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Voyager
Voyager
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Registered: ‎10-21-2015

Hi

When you use SDSoC, have you created direct i/o(axis) interface for your sdsoc platform like this?

https://www.xilinx.com/html_docs/xilinx2019_1/sdsoc_doc/sdsoc-platform-examples-umx1504034375845.html?hl=axis

Similarly, you need to decalre axis port for your Vitis platform by refering to https://www.xilinx.com/html_docs/xilinx2019_2/vitis_doc/Chunk1756746358.html#phl1512685419302

Then connect an axis port of kernel  to the axis port interface of your platform

For that, refer to https://github.com/Xilinx/Vitis_Accel_Examples/tree/master/host/streaming_free_running_kernel/src

https://www.xilinx.com/html_docs/xilinx2019_2/vitis_doc/Chunk1180956723.html#itc1511211457306

 

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Adventurer
Adventurer
369 Views
Registered: ‎06-20-2019

Hi @hokim,
I have not created such platform on SDSoC but I see your point. In that example(free running kernels), it is getting some data from global memory via a kernel and gives it back to the global memory via another kernel. The "increment" kernel is in between. I have deleted the other kernels, not connected the kernel increment to anywhere and that caused this issue. As much as I understand, you need to connect the kernel increment to a kernel or to a platform interface. Otherwise, it won't be compiled. I wasn't aware of those axis port declaration process.

Thank you.

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