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Visitor
Visitor
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Registered: ‎07-09-2020

Transceiver Connectivity in Vitis RTL Kernel using the Vitis compiler connectivity option connect. Explanation missing in UG1393

Hi all,

I am using Vitis 2020.1 and creating an RTL Kernel. I need to connect an ethernet subsystem ports to the board pins.

I have a design that works for U250. to connect the freerun clock in the connectivity  .ini file the following switch is used.

connect=plp_s_aclk_ctrl_00:eth_subsystem0/clk_freerun

It is pretty simple to understand the "connect" switch is used for non-AXI4-stream connectivity, however, there is no explanation of this switch in the reference UG1393.

My question is where can I find the name of the Alveo clock ports for u200 card? I do not know where plp_s_aclk_ctrl_00 is defined for U250 so I can do the same for u200.

I have tried the Vitis "platforminfo" utility. There's no such info there.

Your help is much appreciated.

Raam

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Moderator
Moderator
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Registered: ‎11-04-2010

The input pin ‘clk_gt_freerun’ of the ethernet Kernel will be connected to a 50MHz clock input in the system linking phase of the implementation for the free running GT clock.

To find this 50MHz clock, you can open the bd design of any example design with your target board and use the below command to return the clock port name:

Ex:get_bd_ports -filter {CONFIG.FREQ_HZ == 50000000}

 

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