Hi there,
We are wanting to use all available DDR banks on our FPGA board as a combined memory. In this post below, it talks about only being able to have a kernel work with one DDR bank at a time.
https://forums.xilinx.com/t5/Vitis-SDAccel-and-SDSoC/multiple-memory-banks/m-p/889885#M2607
Is there some IP in Vitis that could allow us to use all for ddr banks as one large memory? Possibly the AXI DMA controller? If not, is there a suggestion of how we could do this?
Thanks
