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Scholar
Scholar
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Registered: ‎06-20-2017

Vitis in SDK mode with strange warning

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Similar to this post, I am seeing the warning:  #warning "There's no DDR_1 in the HW design. MMU translation table marks 32 GB DDR address space as undefined" [-Wcpp].

Is this because the ZCU104 doesn't come with PL DDR?

There are no references to DDR1 in the code.  At first I was thinking it was my linker script which I have modified for the R5, but on closer inspection, I do not think so.

This is my linker script for the R5s.  I am not doing any A53 code as yet.

/*******************************************************************/
/*                                                                 */
/* This file is automatically generated by linker script generator.*/
/*                                                                 */
/* Version: 2019.2                                                 */
/*                                                                 */
/* Copyright (c) 2010-2019 Xilinx, Inc.  All rights reserved.      */
/*                                                                 */
/* Description : Cortex-R5 Linker Script                           */
/*                                                                 */
/*******************************************************************/

_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x2000;
_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x2000;

_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;
_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;
_IRQ_STACK_SIZE = DEFINED(_IRQ_STACK_SIZE) ? _IRQ_STACK_SIZE : 1024;
_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;
_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;

/* Define Memories in the system */

MEMORY
{
   psu_ocm_ram_0_MEM_0     : ORIGIN = 0xFFFC0000, LENGTH = 0x40000
   psu_qspi_linear_0_MEM_0 : ORIGIN = 0xC0000000, LENGTH = 0x20000000
   psu_r5_0_atcm_MEM_0     : ORIGIN = 0x0,        LENGTH = 0x10000
   psu_r5_0_btcm_MEM_0     : ORIGIN = 0x20000,    LENGTH = 0x10000
   DDR_UNUSED              : ORIGIN = 0x100000,   LENGTH = 0xf00000
   R5_DDR_0                : ORIGIN = 0x1000000,  LENGTH  =0x1000000
   R5_DDR_1                : ORIGIN = 0x2000000,  LENGTH = 0x1000000   
   R5_DDR_HEAP_0           : ORIGIN = 0x3000000,  LENGTH  =0x1000000
   R5_DDR_HEAP_1           : ORIGIN = 0x4000000,  LENGTH = 0x1000000     
   DDR_RESERVED            : ORIGIN = 0x5000000,  LENGTH = 0x7B000000   
}

/* Specify the default entry point to the program */

ENTRY(_boot)

/* Define the sections, and where they are mapped in memory */

SECTIONS
{
.vectors : {
   KEEP (*(.vectors))
   *(.boot)
} > psu_r5_0_atcm_MEM_0

.text : {
   *(.text)
   *(.text.*)
   *(.gnu.linkonce.t.*)
   *(.plt)
   *(.gnu_warning)
   *(.gcc_execpt_table)
   *(.glue_7)
   *(.glue_7t)
   *(.vfp11_veneer)
   *(.ARM.extab)
   *(.gnu.linkonce.armextab.*)
} > R5_DDR_0

.init : {
   KEEP (*(.init))
} > R5_DDR_0

.fini : {
   KEEP (*(.fini))
} > R5_DDR_0

.interp : {
   KEEP (*(.interp))
} > R5_DDR_0

.note-ABI-tag : {
   KEEP (*(.note-ABI-tag))
} > R5_DDR_0

.rodata : {
   __rodata_start = .;
   *(.rodata)
   *(.rodata.*)
   *(.gnu.linkonce.r.*)
   __rodata_end = .;
} > R5_DDR_0

.rodata1 : {
   __rodata1_start = .;
   *(.rodata1)
   *(.rodata1.*)
   __rodata1_end = .;
} > R5_DDR_0

.sdata2 : {
   __sdata2_start = .;
   *(.sdata2)
   *(.sdata2.*)
   *(.gnu.linkonce.s2.*)
   __sdata2_end = .;
} > R5_DDR_0

.sbss2 : {
   __sbss2_start = .;
   *(.sbss2)
   *(.sbss2.*)
   *(.gnu.linkonce.sb2.*)
   __sbss2_end = .;
} > R5_DDR_0

.data : {
   __data_start = .;
   *(.data)
   *(.data.*)
   *(.gnu.linkonce.d.*)
   *(.jcr)
   *(.got)
   *(.got.plt)
   __data_end = .;
} > R5_DDR_0

.data1 : {
   __data1_start = .;
   *(.data1)
   *(.data1.*)
   __data1_end = .;
} > R5_DDR_0

.got : {
   *(.got)
} > R5_DDR_0

.ctors : {
   __CTOR_LIST__ = .;
   ___CTORS_LIST___ = .;
   KEEP (*crtbegin.o(.ctors))
   KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
   KEEP (*(SORT(.ctors.*)))
   KEEP (*(.ctors))
   __CTOR_END__ = .;
   ___CTORS_END___ = .;
} > R5_DDR_0

.dtors : {
   __DTOR_LIST__ = .;
   ___DTORS_LIST___ = .;
   KEEP (*crtbegin.o(.dtors))
   KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
   KEEP (*(SORT(.dtors.*)))
   KEEP (*(.dtors))
   __DTOR_END__ = .;
   ___DTORS_END___ = .;
} > R5_DDR_0

.fixup : {
   __fixup_start = .;
   *(.fixup)
   __fixup_end = .;
} > R5_DDR_0

.eh_frame : {
   *(.eh_frame)
} > R5_DDR_0

.eh_framehdr : {
   __eh_framehdr_start = .;
   *(.eh_framehdr)
   __eh_framehdr_end = .;
} > R5_DDR_0

.gcc_except_table : {
   *(.gcc_except_table)
} > R5_DDR_0

.mmu_tbl (ALIGN(16384)) : {
   __mmu_tbl_start = .;
   *(.mmu_tbl)
   __mmu_tbl_end = .;
} > R5_DDR_0

.ARM.exidx : {
   __exidx_start = .;
   *(.ARM.exidx*)
   *(.gnu.linkonce.armexidix.*.*)
   __exidx_end = .;
} > R5_DDR_0

.preinit_array : {
   __preinit_array_start = .;
   KEEP (*(SORT(.preinit_array.*)))
   KEEP (*(.preinit_array))
   __preinit_array_end = .;
} > R5_DDR_0

.init_array : {
   __init_array_start = .;
   KEEP (*(SORT(.init_array.*)))
   KEEP (*(.init_array))
   __init_array_end = .;
} > R5_DDR_0

.fini_array : {
   __fini_array_start = .;
   KEEP (*(SORT(.fini_array.*)))
   KEEP (*(.fini_array))
   __fini_array_end = .;
} > R5_DDR_0

.ARM.attributes : {
   __ARM.attributes_start = .;
   *(.ARM.attributes)
   __ARM.attributes_end = .;
} > R5_DDR_0

.sdata : {
   __sdata_start = .;
   *(.sdata)
   *(.sdata.*)
   *(.gnu.linkonce.s.*)
   __sdata_end = .;
} > R5_DDR_0

.sbss (NOLOAD) : {
   __sbss_start = .;
   *(.sbss)
   *(.sbss.*)
   *(.gnu.linkonce.sb.*)
   __sbss_end = .;
} > R5_DDR_0

.tdata : {
   __tdata_start = .;
   *(.tdata)
   *(.tdata.*)
   *(.gnu.linkonce.td.*)
   __tdata_end = .;
} > R5_DDR_0

.tbss : {
   __tbss_start = .;
   *(.tbss)
   *(.tbss.*)
   *(.gnu.linkonce.tb.*)
   __tbss_end = .;
} > R5_DDR_0

.bss (NOLOAD) : {
   . = ALIGN(4);
   __bss_start__ = .;
   *(.bss)
   *(.bss.*)
   *(.gnu.linkonce.b.*)
   *(COMMON)
   . = ALIGN(4);
   __bss_end__ = .;
} > R5_DDR_0

_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );

_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );

/* Generate Stack and Heap definitions */

.heap (NOLOAD) : {
   . = ALIGN(16);
   _heap = .;
   HeapBase = .;
   _heap_start = .;
   . += _HEAP_SIZE;
   _heap_end = .;
   HeapLimit = .;
} > R5_DDR_HEAP_0

.stack (NOLOAD) : {
   . = ALIGN(16);
   _stack_end = .;
   . += _STACK_SIZE;
   _stack = .;
   __stack = _stack;
   . = ALIGN(16);
   _irq_stack_end = .;
   . += _IRQ_STACK_SIZE;
   __irq_stack = .;
   _supervisor_stack_end = .;
   . += _SUPERVISOR_STACK_SIZE;
   . = ALIGN(16);
   __supervisor_stack = .;
   _abort_stack_end = .;
   . += _ABORT_STACK_SIZE;
   . = ALIGN(16);
   __abort_stack = .;
   _fiq_stack_end = .;
   . += _FIQ_STACK_SIZE;
   . = ALIGN(16);
   __fiq_stack = .;
   _undef_stack_end = .;
   . += _UNDEF_STACK_SIZE;
   . = ALIGN(16);
   __undef_stack = .;
} > R5_DDR_0

_end = .;
}

Mike
1 Solution

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Highlighted
Moderator
Moderator
113 Views
Registered: ‎03-25-2019

Re: Vitis in SDK mode with strange warning

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Hi @maps-mpls,

DDR_1 refer to DDR_HIGH address range.
You can check the DDR_HIGH address in the bellow table taken from UG1085:

ddr.png

The warning "There is no DDR_1 in the HW design" is intended to indicate that there is no memory mapped to higher DDR in the design.

Best regards,
Abdallah
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1 Reply
Highlighted
Moderator
Moderator
114 Views
Registered: ‎03-25-2019

Re: Vitis in SDK mode with strange warning

Jump to solution

Hi @maps-mpls,

DDR_1 refer to DDR_HIGH address range.
You can check the DDR_HIGH address in the bellow table taken from UG1085:

ddr.png

The warning "There is no DDR_1 in the HW design" is intended to indicate that there is no memory mapped to higher DDR in the design.

Best regards,
Abdallah
-------------------------------------------------------------------------------
Please don't forget to reply, kudo and accept as a solution

View solution in original post