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nirdhish
Contributor
Contributor
297 Views
Registered: ‎08-26-2018

Vitis placement causing large net delay

Dear,

My design meets the timing constraints independently, but when implemented in the dynamic logic by Vitis, it fails miserably. The failing path is between the interconnect placed by Vitis and one of the registers in my design. I am new to all this. Any ideas?

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hongh
Moderator
Moderator
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Registered: ‎11-04-2010

Hi, @nirdhish ,

Could you decribe more about your design flow and which device you are using.

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nirdhish
Contributor
Contributor
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Registered: ‎08-26-2018

Hi Hongh, 

I am using Alevo u280. My design flow
1) I create a Vitis project and let it generate an example RTL, Test bench, and an example host program.

2) I modify the example RTL to weave in my custom blocks and then verify it using a modified test bench.

3) I also apply a clock constraint to ap_clk (300 MHz) and run synthesis and Implementation to see if the design meets the timing constraint (It does).

4) I run a post-synthesis functional simulation to verify the correctness of my design.

5) I export the kernel, modify the host application, run HW-emulation and then run the hardware build.

 

My standalone design meets timing. But with the Vitis flow, the interconnect inserted by the Vitis is placed far from my design, causing a considerable path delay. I am not sure how to direct Vitis to place the interconnect closer to my design.

 

Thank you for your help.

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