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skotti
Observer
Observer
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Registered: ‎06-18-2018

What is the meaning of Loop Pipeline Activity metric?

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What does Loop Pipeline Activity metric mean in SDx Application Timeline?

It is not described well in documentation.

Whether it means how much all pipeline structure , built in fpga, works and when this structure is active? Or something else?

The file with an example graph is attached.

Screenshot from 2018-07-04 15-26-18.png
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graces
Moderator
Moderator
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Registered: ‎07-16-2008

This section is showing the activity for all pipeline regions for each Compute Unit. 

As I understand it, if the pipeline enable signal is high, there is data in the pipeline and pipeline is processing data, and vice versa. 

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Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs.
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graces
Moderator
Moderator
912 Views
Registered: ‎07-16-2008

This section is showing the activity for all pipeline regions for each Compute Unit. 

As I understand it, if the pipeline enable signal is high, there is data in the pipeline and pipeline is processing data, and vice versa. 

-----------------------------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs.
-----------------------------------------------------------------------------------------------------------------------

View solution in original post