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Jain
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Registered: ‎06-30-2020

Xilinx/Vitis + Zybo Z7-20 Pcam 5C

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Sorry Xilinx my last post was marked as spam so I repost it again to hope anyone else can help me soon
 
 
Xilinx/Vitis + Zybo Z7-20 Pcam 5C
 

In the group, have someone try to Zybo Z7-20 Pcam 5C project with Vitis

I tried to use Zybo Z7-20 Pcam 5C Demo Vivado 2019.1-1 + SDK project in my Vivado + Vitis 2019. It's not easy like I think. 

Link project: https://github.com/Digilent/Zybo-Z7-20-pcam-5c/releases/tag/v2019.1-1

Firstly, I use Vivado 2019 to load this project. It requires I have to update the IP block because the older version exists. After that, I have done to build my bitstream except slack timing like image. But no big deal I just want to try it run on Vitis soft first. And then, I exported hardware file with a bitstream

report zyqn pcam.PNG

 Timing has worst slack

timing error.PNG

 

 
 
 
I launch Vitis 2019 version, created a platform project with my hardware XSA file and application project with  "Empty Application".
Right-click on the "src" subdirectory of the application project and import the SDK folder, then try to build the project again like the pic below.
vitis 1.PNG
After, I got some error like images below, I guess the reasons are in Vitis and SDK have some different platform. I did anything but still solved its problem. Have someone help me. Thank for reading.
error 1.PNG

Nothing to build in platform 'ZYQN_PCAM5'

13:28:28 **** Incremental Build of configuration Debug for project zybo_z7_pcam5 ****
make all
make --no-print-directory pre-build
a9-linaro-pre-build-step
' '
make --no-print-directory main-build
make[1]: *** No rule to make target '../src/lscript.ld', needed by 'zybo_z7_pcam5.elf'. Stop.
make: *** [makefile:34: all] Error 2

13:28:29 Build Finished (took 1s.697ms)

13:28:31 **** Incremental Build of configuration Debug for project zybo_z7_pcam5_system ****
make all
Generating bif file for the system project
generate_system_bif.bat 20793 C:/Users/HPZBOOK15G3/workspace/ZYQN_PCAM5/export/ZYQN_PCAM5/ZYQN_PCAM5.xpfm standalone_domain C:/Users/HPZBOOK15G3/workspace/zybo_z7_pcam5_system/Debug/system.bif
sdcard_gen --xpfm C:/Users/HPZBOOK15G3/workspace/ZYQN_PCAM5/export/ZYQN_PCAM5/ZYQN_PCAM5.xpfm --sys_config ZYQN_PCAM5 --bif C:/Users/HPZBOOK15G3/workspace/zybo_z7_pcam5_system/Debug/system.bif --no_bitstream --elf C:/Users/HPZBOOK15G3/workspace/zybo_z7_pcam5/Debug/zybo_z7_pcam5.elf,ps7_cortexa9_0
ELF does not exist: C:/Users/HPZBOOK15G3/workspace/zybo_z7_pcam5/Debug/zybo_z7_pcam5.elf
make: *** [makefile:36: sd_card] Error 1

13:28:37 Build Finished (took 6s.390ms)

 

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Jain
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Registered: ‎06-30-2020

Thank for reading my post. I was successful to rebuild Zybo Z7-20 Pcam 5C  + SDK to

Vitis + Zybo Z7-20 Pcam 5C. My fault is not to follow exactly the instructions README in the zip file.

Someone got the same problem as me, I give some suggestions to save your time.

After update IP and rebuild to get new file bitstream .xsa, I exported hardware include bitstream and launch on Vitis.

In Vitis, file -> new -> platform project with .xsa file. To make sure your hardware file can be linked to the data folder, let's try to "build project" for the platform file. If has errors,  try to "update hardware specification" -> "clean project" -> " build project". If it still has errors, I think it's because your file location or vivado filename project too long and deep, makes location file, and filename simple. As for me, I save vivado file in C:/VIVADO and filename "zybo_pcam5c" 

Next, create 'Application project' make sure your target language is C++, If you don't set C++ language, your project will appear with some error.

 Connect the zybo board with your laptop, open tera term  set 112500baud rate,

In vitis tool bar, Xilinx -> program FPGA make sure your bitstream file correctly.

Finally, "Run as" -> "launch on hardware" and watch your good job on tera term.

I hope it saves your time

zybo z7 20 pcam5c.PNG

 

 

 

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Jain
Visitor
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Registered: ‎06-30-2020

Thank for reading my post. I was successful to rebuild Zybo Z7-20 Pcam 5C  + SDK to

Vitis + Zybo Z7-20 Pcam 5C. My fault is not to follow exactly the instructions README in the zip file.

Someone got the same problem as me, I give some suggestions to save your time.

After update IP and rebuild to get new file bitstream .xsa, I exported hardware include bitstream and launch on Vitis.

In Vitis, file -> new -> platform project with .xsa file. To make sure your hardware file can be linked to the data folder, let's try to "build project" for the platform file. If has errors,  try to "update hardware specification" -> "clean project" -> " build project". If it still has errors, I think it's because your file location or vivado filename project too long and deep, makes location file, and filename simple. As for me, I save vivado file in C:/VIVADO and filename "zybo_pcam5c" 

Next, create 'Application project' make sure your target language is C++, If you don't set C++ language, your project will appear with some error.

 Connect the zybo board with your laptop, open tera term  set 112500baud rate,

In vitis tool bar, Xilinx -> program FPGA make sure your bitstream file correctly.

Finally, "Run as" -> "launch on hardware" and watch your good job on tera term.

I hope it saves your time

zybo z7 20 pcam5c.PNG

 

 

 

View solution in original post

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