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benedetto73
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Registered: ‎09-30-2019

dataflow check failed despite pragma stable

I need to scan two separate regions of same big array and extracts two stream out of them.
Despite the fact that I mark that region as "stable", I get a dataflow check error.

Any idea?

Xilinx Vitis IDE v2019.2 (64-bit)
SW Build 2708876 on Wed Nov 6 21:40:25 MST 2019

 

void kernel(int * mem, int size,...)
{
#pragma HLS INTERFACE m_axi port = mem offset = slave bundle = hbm0
#pragma HLS INTERFACE s_axilite port = mem bundle = control
#pragma HLS INTERFACE s_axilite port = return bundle = control
#pragma HLS INTERFACE s_axilite port = size bundle = control


static hls::stream<int> Rstream("Rstream");
static hls::stream<int> Lstream("Lstream");
#pragma HLS stream variable=Rstream depth=16
#pragma HLS stream variable=Lstream depth=16

#pragma HLS DATAFLOW
#pragma HLS stable variable=mem

readAndCreateStream(mem,          size/2, Lstream);
readAndCreateStream(&mem[size/2], size/2, Rstream);
computeStreams(Lstream, Rstream, outputStream);

// ....
}

 

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yhy.xilinx
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Registered: ‎06-20-2019

Your FIFO depth may not be sufficient, you must use set_directive_stream directive.
Also check, page 215 of:
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug902-vivado-high-level-synthesis.pdf
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benedetto73
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Registered: ‎09-30-2019

Thanks @yhy.xilinx ,
I will try that as soon as possible.

However, if that's the case, please file a bug for "misleading diagnostic message" to the compiler guys.

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yhy.xilinx
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Registered: ‎06-20-2019

You can also use : #pragma HLS STREAM variable=your_var depth=(the depth you want, must be more than 2, try big numbers to be conservative)

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benedetto73
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Registered: ‎09-30-2019

Hi @yhy.xilinx .

Adding the "depth" attribute doesn't fix the issue.
Any other suggestion?

 

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yhy.xilinx
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Registered: ‎06-20-2019

I am not really sure if my code would help but these worked for me:

void inc(hls::stream<ap_axiu<64, 0, 0, 0> >& input, hls::stream<ap_axiu<32, 0, 0, 0> >& output)
{
#pragma HLS interface axis port=input
#pragma HLS interface axis port=output
#pragma HLS interface ap_ctrl_none port=return

hls::stream<ap_axiu<64, 0, 0, 0> > in;
hls::stream<ap_axiu<32, 0, 0, 0> > out;

#pragma HLS STREAM variable=in depth=1024
#pragma HLS STREAM variable=out depth=1024
...
}
Seems like the difference with your is the keyword static which I do not expect it to be problem but since it is signed as a global during compiling maybe it cannot be handled with a FIFO instead of RAM. Moreover, if you have some stream parameter, you must be sure that axis is utilized.

I hope that this helps.
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benedetto73
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Registered: ‎09-30-2019

Thanks @yhy.xilinx , but your code splits two streams coming out the same array.

My streams come out 2 different parts of the same array.
Example:
- stream 1 comes out array[0];
- stream 2 comes out array[n];

Where 'n' actually changes at every iteration of the outer loop...

 

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