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mathmaxsean
Explorer
Explorer
1,027 Views
Registered: ‎05-23-2017

how to find the finnally clock frequency of the kernel after compilation targeting hardware?

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I used the below way to change the default kernel target clock frequency:

"Setting period in a tcl file and execute it before hls:

TCL hls_hook.tcl content:  create_clock -period 350MHz  -name default

option: --xp prop:solution.hls_pre_tcl=hls_hook.tcl

"

I use this way to change the default clock 300 Mhz to 350 Mhz.

From the "vivado_hls.log" I can see that the clock was changed successfully.

NFO: [HLS 200-10] Setting target device to 'xcvu9p-fsgd2104-2-i'
INFO: [SYN 201-201] Setting up clock 'default' with a period of 3.33333ns.
INFO: [HLS 200-435] Setting 'config_sdx -optimization_level' configuration: config_rtl -vivado_phys_opt=none
INFO: [HLS 200-435] Setting 'config_sdx -optimization_level' configuration: config_bind -effort=medium
INFO: [HLS 200-435] Setting 'config_sdx -optimization_level' configuration: config_schedule -effort=medium
INFO: [HLS 200-435] Setting 'config_sdx -profile' configuration: config_rtl -stall_sig_gen=1
INFO: [HLS 200-435] Setting 'config_sdx -profile' configuration: config_rtl -profile=1
INFO: [HLS 200-435] Setting 'config_sdx -target' configuration: config_compile -pipeline_loops=64
INFO: [XFORM 203-1171] Pipeline the innermost loop with trip count more than 64 or its parent loop when its trip count is less than or equal 64.
INFO: [HLS 200-435] Setting 'config_sdx -target' configuration: config_compile -name_max_length=256
INFO: [XFORM 203-1161] The maximum of name length is set into 256.
INFO: [HLS 200-435] Setting 'config_sdx -target' configuration: config_schedule -relax_ii_for_timing=1
INFO: [HLS 200-435] Setting 'config_sdx -target' configuration: config_rtl -register_reset_num=3
INFO: [HLS 200-435] Setting 'config_sdx -target' configuration: config_rtl -auto_prefix=1
INFO: [HLS 200-435] Setting 'config_sdx -target' configuration: set_clock_uncertainty 27%
INFO: [SYN 201-201] Setting up clock 'default' with an uncertainty of 0.9ns.
INFO: [SYN 201-201] Setting up clock 'default' with an uncertainty of 0.285667ns.
INFO: [SYN 201-201] Setting up clock 'default' with a period of 2.85714ns.
INFO: [SCHED 204-61] Option 'relax_ii_for_timing' is enabled, will increase II to preserve clock frequency constraints.

I also changed the report from "pcaf_fpga.hw.xilinx_vcu1525_dynamic_5_1/system_estimate_pcaf_fpga.hw.xilinx_vcu1525_dynamic_5_1.xtxt":

===============================================================================
Version:    xocc v2018.2_EA2236721 (64-bit)
Build:      SW Build 2236721 on Sun May 20 18:49:47 MDT 2018
Copyright:  Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
Created:    Thu Dec  6 21:19:07 2018
===============================================================================

-------------------------------------------------------------------------------
Design Name:             pcaf_fpga.hw.xilinx_vcu1525_dynamic_5_1
Target Device:           xilinx:vcu1525:dynamic:5.1
Target Clock:            300.000000MHzTotal number of kernels: 1
-------------------------------------------------------------------------------

Kernel Summary
Kernel Name  Type  Target              OpenCL Library                           Compute Units
-----------  ----  ------------------  ---------------------------------------  -------------
pcaf_fpga    c     fpga0:OCL_REGION_0  pcaf_fpga.hw.xilinx_vcu1525_dynamic_5_1  1


-------------------------------------------------------------------------------
OpenCL Binary:     pcaf_fpga.hw.xilinx_vcu1525_dynamic_5_1
Kernels mapped to: clc_region

Timing Information (MHz)
Compute Unit  Kernel Name  Module Name               Target Frequency  Estimated Frequency
------------  -----------  ------------------------  ----------------  -------------------
pcaf_fpga_1   pcaf_fpga    read_query_pca            349.65036         388.953705
pcaf_fpga_1   pcaf_fpga    read_query_or             349.65036         388.953705
pcaf_fpga_1   pcaf_fpga    d_copy_g2oc_queries       349.65036         388.953705
pcaf_fpga_1   pcaf_fpga    query_cop_g2oc            349.65036         388.953705
pcaf_fpga_1   pcaf_fpga    filtering_entry596615     349.65036         777.60498
pcaf_fpga_1   pcaf_fpga    read_feature_pca          349.65036         388.953705
pcaf_fpga_1   pcaf_fpga    d_copy_g2oc_pca_features  349.65036         388.953705
pcaf_fpga_1   pcaf_fpga    filtering_Block_proc5964  349.65036         777.60498
pcaf_fpga_1   pcaf_fpga    dist_calc_PCA             349.65036         432.900452
pcaf_fpga_1   pcaf_fpga    read_feature_or           349.65036         388.953705

But the target frequency still shows as an 300 Mhz, whereras the target frequency changed to 350Mhz.

It's very consufing.

I wonder is there a report can tell me what is the final frequency of the kernel be assigned?

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hongh
Moderator
Moderator
980 Views
Registered: ‎11-04-2010

Hi, @mathmaxsean ,

1. You can try in 2018.3. I have seen option "--kernel_frequency 350" can work successfully in SDx.

2. "Target Frequency 349.65036" for kernel also means the workaround has worked properly.

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hongh
Moderator
Moderator
981 Views
Registered: ‎11-04-2010

Hi, @mathmaxsean ,

1. You can try in 2018.3. I have seen option "--kernel_frequency 350" can work successfully in SDx.

2. "Target Frequency 349.65036" for kernel also means the workaround has worked properly.

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

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mathmaxsean
Explorer
Explorer
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Registered: ‎05-23-2017

@hongh

I checked the report from the hw compilation. It says targeting a 400Mhz frequency.

 

Timing Information (MHz)
Compute Unit  Kernel Name  Module Name               Target Frequency  Estimated Frequency
------------  -----------  ------------------------  ----------------  -------------------
pcaf_fpga_1   pcaf_fpga    read_query_pca            400               444.444458
pcaf_fpga_1   pcaf_fpga    read_query_or             400               444.444458
pcaf_fpga_1   pcaf_fpga    d_copy_g2oc_queries       400               444.444458
pcaf_fpga_1   pcaf_fpga    query_cop_g2oc            400               444.444458
pcaf_fpga_1   pcaf_fpga    filtering_entry20517      400               888.888916
pcaf_fpga_1   pcaf_fpga    read_feature_pca          400               444.444458
pcaf_fpga_1   pcaf_fpga    d_copy_g2oc_pca_features  400               444.444458
pcaf_fpga_1   pcaf_fpga    filtering_Block_proc203   400               581.733582
pcaf_fpga_1   pcaf_fpga    init_heaps                400               1658.37488
pcaf_fpga_1   pcaf_fpga    dist_calc_PCA             400               446.62793
pcaf_fpga_1   pcaf_fpga    read_feature_or           400               444.444458
pcaf_fpga_1   pcaf_fpga    dist_calc_or1             400               464.46817
pcaf_fpga_1   pcaf_fpga    dist_calc_or2             400               446.62793
pcaf_fpga_1   pcaf_fpga    dist_calc_or              400               446.62793
pcaf_fpga_1   pcaf_fpga    k_max                     400               542.005432
pcaf_fpga_1   pcaf_fpga    dist_calc_pcaf            400               444.444458
pcaf_fpga_1   pcaf_fpga    filter_sum                400               517.063049
pcaf_fpga_1   pcaf_fpga    filtering                 400               444.444458
pcaf_fpga_1   pcaf_fpga    d_copy_oc2g               400               444.444458
pcaf_fpga_1   pcaf_fpga    pcaf_fpga                 400               444.444458

But from the sdaccel_profile_summary.html report I can see the clock frequency is still 300 Mhz which is the default.

Why?

What's the exact frequency for my final design?

 

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