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Registered: ‎11-28-2018

hw emulation failed for RTL kernel

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Hi!

I try to run HW - Emulation for my RTL Kernel. I used RTL Kernel Wizard for generating files, then i inserted own core in Wrapper. Simulation is succesful, Synthesis too (there is no significant warnings). But now Error appears during Emulation-HW.

There is next message in console:

[

 INFO: [VPL 60-251] Hardware accelerator integration...
ERROR: [VPL 60-399] vivado failed, please see log file for detail: '/home/sadriev/Desktop/projects/fir_cmplx/Emulation-HW/binary_container_1/link/vivado/vivado.log'
ERROR: [VPL 60-806] Failed to finish platform linker
ERROR: [XOCC 60-398] vpl failed
ERROR: [XOCC 60-626] Kernel link failed to complete
ERROR: [XOCC 60-703] Failed to finish linking
makefile:77: recipe for target 'binary_container_1.xclbin' failed
make: *** [binary_container_1.xclbin] Error 1

]

Message send to Emulation-HW/binary_container_1/link/vivado/vivado.log

[

launch_simulation: Time (s): cpu = 00:00:09 ; elapsed = 00:00:28 . Memory (MB): peak = 2375.145 ; gain = 17.484 ; free physical = 4410 ; free virtual = 34481
INFO: [Vivado 12-5680] Creating behavioral simulation scripts in '/home/sadriev/Desktop/projects/fir_cmplx/Emulation-HW/binary_container_1/link/vivado/prj/prj.sim/sim_1/behav/xsim'
INFO: [Vivado 12-5425] Xilinx recommends using the export_simulation Tcl command for generating simulation scripts to use outside of the Vivado environment. Please see 'Logic Simulation' user guide UG900 for details on how to use this command.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/mnt/data/soft/Xilinx/Vivado/2018.2/data/xsim/xsim.ini' copied to run dir:'/home/sadriev/Desktop/projects/fir_cmplx/Emulation-HW/binary_container_1/link/vivado/prj/prj.sim/sim_1/behav/xsim'
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-60] Script generated:/home/sadriev/Desktop/projects/fir_cmplx/Emulation-HW/binary_container_1/link/vivado/prj/prj.sim/sim_1/behav/xsim/compile.sh
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-60] Script generated:/home/sadriev/Desktop/projects/fir_cmplx/Emulation-HW/binary_container_1/link/vivado/prj/prj.sim/sim_1/behav/xsim/elaborate.sh
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-60] Script generated:/home/sadriev/Desktop/projects/fir_cmplx/Emulation-HW/binary_container_1/link/vivado/prj/prj.sim/sim_1/behav/xsim/simulate.sh
launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:13 . Memory (MB): peak = 2375.145 ; gain = 0.000 ; free physical = 4306 ; free virtual = 33204
error renaming "simulate_sysemulation.sh" to "simulate.sh": no such file or directory
while executing
"file rename -force simulate_sysemulation.sh simulate.sh"
(procedure "writeNewSimulateScript" line 13)
invoked from within
"writeNewSimulateScript $replaceXSimCall $bdName"
(procedure "hw_em_common_util::generate_simulation_scripts_and_compile" line 118)
invoked from within
"hw_em_common_util::generate_simulation_scripts_and_compile $config_info"
(procedure "hw_em_util::generate_simulation_scripts_and_compile" line 2)
invoked from within
"hw_em_util::generate_simulation_scripts_and_compile $config_info"
(file "/home/sadriev/Desktop/projects/fir_cmplx/Emulation-HW/binary_container_1/link/vivado/ipirun.tcl" line 202)
INFO: [Common 17-206] Exiting Vivado at Wed Nov 28 18:10:31 2018...

 ]

Any idea how to fix it?

Thank you in advance

 

 

 

 

 

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1 Solution

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Highlighted
761 Views
Registered: ‎11-28-2018

Thank you! i could not share project.

The problem was solved by the next actions

Before my project was compiled on mounted disk and i had Error above.

After that i moved project to local Linux disk and problem is dissapeared.

I can not explain the reason

View solution in original post

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6 Replies
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Xilinx Employee
Xilinx Employee
865 Views
Registered: ‎07-16-2008

Are you running the latest 2018.2?

Is it possible to share the test case for a look?

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
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Highlighted
855 Views
Registered: ‎11-28-2018
there is not latest version. Version from 18 June 2018.
What do you mean under test case? Do you mean share RTL files? I can not share it
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Highlighted
Xilinx Employee
Xilinx Employee
847 Views
Registered: ‎07-16-2008

Would you please give it a try in 2018.2_XDF release?

For test case, I mean the SDAccel project, where the RTL kernel is added as .xo.

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
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Highlighted
844 Views
Registered: ‎11-28-2018

According to the page 

https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/sdaccel-development-environment/2018-2-xdf.html

This release is dedicated to the development of applications for the Alveo cards (U200 and U250).  For other platforms please use the regular 2018.2 release of SDAccel.  "

I am using vcu1525.

Unfortunately, I can not share project

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Highlighted
Xilinx Employee
Xilinx Employee
805 Views
Registered: ‎07-16-2008

This looks to be a design specific issue. I haven't come across the same issue with RTL kernel.

If it's possible to share the test project, I can send you an EzMove link to transfer the file without attaching it to the post.

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Highlighted
762 Views
Registered: ‎11-28-2018

Thank you! i could not share project.

The problem was solved by the next actions

Before my project was compiled on mounted disk and i had Error above.

After that i moved project to local Linux disk and problem is dissapeared.

I can not explain the reason

View solution in original post

0 Kudos