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anto95
Participant
Participant
1,477 Views
Registered: ‎07-17-2017

sdsoc build error with zero_copy pragmas

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Hi all, 

i'm trying to build a big project with sdsoc, i have a task that has to be executed in fpga. The hardware function, fpga_top, it's in a loop and has to be called multiple times.

 

for(int i = 0; i < nimages; ++i){

	...
        
       // Offload Calculation to FPGA
	#pragma SDS resource(1)
        fpga_top(layer, (data_t *)SHARED_DRAM, (data_t *)SHARED_BUFFER, weights_offset, num_weights,
				 input_offset, datasize, nimages);

... }

 

 

The fpga_top function is defined in another file in this way: 

 

#pragma SDS data mem_attribute(SHARED_DRAM:NON_PHYSICAL_CONTIGUOUS)
#pragma SDS data mem_attribute(SHARED_BUFFER:NON_PHYSICAL_CONTIGUOUS)
#pragma SDS zero_copy(SHARED_DRAM[0:datasize*4/nimages])
#pragma SDS zero_copy(SHARED_BUFFER[0:datasize*4])

void fpga_top(layer_t layer, data_t *SHARED_DRAM, data_t *SHARED_BUFFER, unsigned int weights_offset,
              weightaddr_t num_weights, unsigned int input_offset, int datasize, int nimages) {

//#pragma HLS INTERFACE m_axi port = SHARED_DRAM   offset = slave bundle = memorybus register
//#pragma HLS INTERFACE m_axi port = SHARED_BUFFER offset = slave bundle = memorybus register

#pragma HLS INTERFACE s_axilite port = layer bundle = axilite  register
#pragma HLS INTERFACE s_axilite port = num_weights bundle = axilite  register
#pragma HLS INTERFACE s_axilite port = weights_offset bundle = axilite  register
#pragma HLS INTERFACE s_axilite port = input_offset bundle = axilite  register
#pragma HLS INTERFACE s_axilite port = return bundle = axilite  register


With sdsoc i've deleted the #pragma HLS directives for the master ports and replaced them with #pragma SDS zero_copy, but when i build the project it gives me this error: 

 

 

fpga_top.cpp:825:13: error: data or monitor or async or resource or wait expected (SDSoC)
fpga_top.cpp:826:13: error: data or monitor or async or resource or wait expected (SDSoC)
ERROR: [SdsCompiler 83-5005] clang exited with non-zero code processing /home/anto/Documenti/sdx_workspace/zynqnet/src/fpga_top.cpp

the lines 825 and 826 are the two lines in wich are present the zero_copy pragmas. 

Can anyone help me to get through this?

 

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skalicky
Explorer
Explorer
1,796 Views
Registered: ‎09-19-2017
Hi,

#pragma SDS zero_copy

should be:

#pragma SDS data zero_copy

per the UG1027 pg. 102 (bottom) (heres the 2017.4 version: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1027-sdsoc-user-guide.pdf)

Sam

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2 Replies
skalicky
Explorer
Explorer
1,797 Views
Registered: ‎09-19-2017
Hi,

#pragma SDS zero_copy

should be:

#pragma SDS data zero_copy

per the UG1027 pg. 102 (bottom) (heres the 2017.4 version: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1027-sdsoc-user-guide.pdf)

Sam

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anto95
Participant
Participant
1,440 Views
Registered: ‎07-17-2017

Thanks @skalicky for the reply, 

you are right, i've made this bad "typing" mistake. 

I've also had to remove the s_axilite HLS pragmas in order to make it synthetize, but now it works. 

 

Thanks again, 

Antonio. 

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