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pmaurice
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Registered: ‎10-16-2020

trying to compile vitis project using accelerated platform

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make -j4 incremental
/Xilinx/Vitis/2020.1/bin/v++ --target hw_emu --link --config common-config.cfg --config binary_container_1-link.cfg -o"binary_container_1.xclbin" binary_container_1.build/krnl_vadd.xo
Option Map File Used: '/Xilinx/Vitis/2020.1/data/vitis/vpp/optMap.xml'

****** v++ v2020.1 (64-bit)
**** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

INFO: [v++ 60-1306] Additional information associated with this v++ link can be found at:
Reports: /root/workspace/truc/Emulation-HW/binary_container_1.build/reports/link
Log files: /root/workspace/truc/Emulation-HW/binary_container_1.build/logs/link
INFO: [v++ 60-1657] Initializing dispatch client.
Running Dispatch Server on port:38617
INFO: [v++ 60-1548] Creating build summary session with primary output /root/workspace/truc/Emulation-HW/binary_container_1.xclbin.link_summary, at Fri Oct 16 15:26:51 2020
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Fri Oct 16 15:26:51 2020
INFO: [v++ 60-895] Target platform: /root/workspace/testacce/export/testacce/testacce.xpfm
INFO: [v++ 60-1578] This platform contains Xilinx Shell Archive '/root/workspace/testacce/export/testacce/hw/system_top2.xsa'
INFO: [v++ 60-629] Linking for hardware emulation target
INFO: [v++ 60-423] Target device: testacce
INFO: [v++ 60-1332] Run 'run_link' status: Not started
INFO: [v++ 60-1443] [15:26:51] Run run_link: Step system_link: Started
INFO: [v++ 60-1453] Command Line: system_link --xo /root/workspace/truc/Emulation-HW/binary_container_1.build/krnl_vadd.xo -keep --config /root/workspace/truc/Emulation-HW/binary_container_1.build/link/int/syslinkConfig.ini --xpfm /root/workspace/testacce/export/testacce/testacce.xpfm --target emu --output_dir /root/workspace/truc/Emulation-HW/binary_container_1.build/link/int --temp_dir /root/workspace/truc/Emulation-HW/binary_container_1.build/link/sys_link
INFO: [v++ 60-1454] Run Directory: /root/workspace/truc/Emulation-HW/binary_container_1.build/link/run_link
INFO: [SYSTEM_LINK 60-1316] Initiating connection to rulecheck server, at Fri Oct 16 15:26:53 2020
INFO: [SYSTEM_LINK 82-70] Extracting xo v3 file /root/workspace/truc/Emulation-HW/binary_container_1.build/krnl_vadd.xo
INFO: [SYSTEM_LINK 82-53] Creating IP database /root/workspace/truc/Emulation-HW/binary_container_1.build/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-38] [15:26:53] build_xd_ip_db started: /Xilinx/Vitis/2020.1/bin/build_xd_ip_db -ip_search 0 -sds-pf /root/workspace/truc/Emulation-HW/binary_container_1.build/link/sys_link/system_top2.hpfm -clkid 0 -ip /root/workspace/truc/Emulation-HW/binary_container_1.build/link/sys_link/iprepo/xilinx_com_hls_krnl_vadd_1_0,krnl_vadd -o /root/workspace/truc/Emulation-HW/binary_container_1.build/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-37] [15:26:57] build_xd_ip_db finished successfully
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1401.164 ; gain = 0.000 ; free physical = 3935 ; free virtual = 5074
INFO: [SYSTEM_LINK 82-51] Create system connectivity graph
INFO: [SYSTEM_LINK 82-102] Applying explicit connections to the system connectivity graph: /root/workspace/truc/Emulation-HW/binary_container_1.build/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [SYSTEM_LINK 82-38] [15:26:57] cfgen started: /Xilinx/Vitis/2020.1/bin/cfgen -nk krnl_vadd:1:krnl_vadd_1 -dmclkid 0 -r /root/workspace/truc/Emulation-HW/binary_container_1.build/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o /root/workspace/truc/Emulation-HW/binary_container_1.build/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [CFGEN 83-0] Kernel Specs:
INFO: [CFGEN 83-0] kernel: krnl_vadd, num: 1 {krnl_vadd_1}
ERROR: [CFGEN 83-2204] No available slave interface on name

ERROR: [SYSTEM_LINK 82-36] [15:26:57] cfgen failed
Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.13 . Memory (MB): peak = 1401.164 ; gain = 0.000 ; free physical = 3932 ; free virtual = 5073
ERROR: [SYSTEM_LINK 82-62] Error generating design file for /root/workspace/truc/Emulation-HW/binary_container_1.build/link/sys_link/cfgraph/cfgen_cfgraph.xml, command: /Xilinx/Vitis/2020.1/bin/cfgen -nk krnl_vadd:1:krnl_vadd_1 -dmclkid 0 -r /root/workspace/truc/Emulation-HW/binary_container_1.build/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o /root/workspace/truc/Emulation-HW/binary_container_1.build/link/sys_link/cfgraph/cfgen_cfgraph.xml
ERROR: [SYSTEM_LINK 82-96] Error applying explicit connections to the system connectivity graph
ERROR: [SYSTEM_LINK 82-79] Unable to create system connectivity graph
INFO: [v++ 60-1442] [15:26:57] Run run_link: Step system_link: Failed
Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1436.820 ; gain = 0.000 ; free physical = 3958 ; free virtual = 5099
ERROR: [v++ 60-661] v++ link run 'run_link' failed
ERROR: [v++ 60-626] Kernel link failed to complete
ERROR: [v++ 60-703] Failed to finish linking
INFO: [v++ 60-1653] Closing dispatch client.
make: *** [binary_container_1.xclbin] Error 1

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pmaurice
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Registered: ‎10-16-2020

answer provided from graces really didn't helped !!!!!!!!!!!!!!!!!!!

View solution in original post

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graces
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Registered: ‎07-16-2008

It looks to be a custom platform. 

INFO: [v++ 60-895] Target platform: /root/workspace/testacce/export/testacce/testacce.xpfm

INFO: [CFGEN 83-0] kernel: krnl_vadd, num: 1 {krnl_vadd_1}
ERROR: [CFGEN 83-2204] No available slave interface on name

If no such error in Xilinx provided platform, that should be a problem with your platform creation. Note we only support embedded custom platform.

 

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pmaurice
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Registered: ‎10-16-2020

Yes this is a custum board, we have bought enclustra's mercury xu9 board.

it is listed on xilinx's website : https://www.xilinx.com/products/boards-and-kits/1-14vidhy.html

I have attempted to create a accelerated platform using template project of vector addition.

I have generated images and stuff using petalinux and then I have linked everything with the platform (sysroot , kernel image , bif files and qemu paths)

I am not really sure what to do to make this works.

I haven't saw any complete tutorial to help to achieve anything using accelerated platform, there is few guideline and theory in your documentation paper but I haven't found anything useful.

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stephenm
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Registered: ‎09-12-2007

The issue is in the V++ is doesnt not know how to link the accelerated portion of your design as you have not provided the correct AXI PFM.

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Creating-an-Acceleration-Platform-for-Vitis-Part-One-Creating/ba-p/1138208

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pmaurice
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Registered: ‎10-16-2020

I clearly have trouble to create the project in vivado to be proper accelerated.

I have followed the tutorial you linked and tried many things (because it's not really well explained and detailed) and everything is a failure.

I don't know what else to do .

 

 

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pmaurice
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Registered: ‎10-16-2020

answer provided from graces really didn't helped !!!!!!!!!!!!!!!!!!!

View solution in original post

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