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Visitor
Visitor
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Registered: ‎09-24-2020

.xo packaging

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Hi, Based on ug1393 chapter "RTL Kernels" A control interface including a start, done and idle is mandatory for kernel to be packaged properly.

1) Assuming the Kernel uses only AXI-Stream interface. what is the purpose  of such a control port? The whole purpose of AXI-stream is having a continues stream enabled by TREADY. No need for start or done.
What should I do with these ports?

2) Are these ports actually the S-AXI4-LITE ports? If so, how are these ports used with AXI-4-LITE interface? 

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Xilinx Employee
Xilinx Employee
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Registered: ‎01-04-2013

The RTL Kernel wizard supports the ap_ctrl_none protocol and does not require the control signals. You can use this for streaming kernels as described here:

https://www.xilinx.com/html_docs/xilinx2020_1/vitis_doc/streamingconnections.html#uug1556136182736

 

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Adventurer
Adventurer
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Registered: ‎03-01-2020

"Streaming" data from host to FPGA is only supported with QDMA platforms which are only available for a limited set of Xilinx boards and the platforms are not publicly distributed by Xilinx. With the standard XDMA platforms, only memory mapped and AXI lite interfaces are supported. Moreover, I am not sure if RTL kernels are supported with QDMA platforms. You should probably contact your Xilinx FAE for information.

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Visitor
Visitor
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Registered: ‎09-24-2020

The host in my case is the AIE, which does support streaming interface.

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Xilinx Employee
Xilinx Employee
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Registered: ‎01-04-2013

The RTL Kernel wizard supports the ap_ctrl_none protocol and does not require the control signals. You can use this for streaming kernels as described here:

https://www.xilinx.com/html_docs/xilinx2020_1/vitis_doc/streamingconnections.html#uug1556136182736

 

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