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Visitor
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413 次查看
注册日期: ‎06-30-2020

关于dataflow数据流中有的fifo空有的fifo满的问题如何解决?

//====================================================================================

报错的问题感觉上是数据流的问题,有的空有的满,但不知如何解决?

不知这种情况可否用综合优化的方式解决?如何解决?

试验目的:将流中的图片复制两份,一份求像素的平均值,然后将平均值给另一份图片做变换处理,

////////////////////////////////////////////////////////////////////////////////////
// Inter-Transaction Progress: Completed Transaction / Total Transaction
// Intra-Transaction Progress: Measured Latency / Latency Estimation * 100%
//
// RTL Simulation : "Inter-Transaction Progress" ["Intra-Transaction Progress"] @ "Simulation Time"
////////////////////////////////////////////////////////////////////////////////////
// RTL Simulation : 0 / 1 [n/a] @ "125000"

//////////////////////////////////////////////////////////////////////////////
// ERROR!!! DEADLOCK DETECTED at 260000 ns! SIMULATION WILL BE STOPPED! //
//////////////////////////////////////////////////////////////////////////////
/////////////////////////
// Dependence cycle 1:
// (1): Process: System_VPSS.Split_U0
// Channel: System_VPSS.srcImg0_data_stream_s_U, EMPTY
// Channel: System_VPSS.srcImg0_data_stream_1_U, EMPTY
// Channel: System_VPSS.srcImg0_data_stream_2_U, EMPTY
// (2): Process: System_VPSS.Duplicate_U0
// Channel: System_VPSS.srcImg1_data_stream_s_U, FULL
// Channel: System_VPSS.srcImg1_data_stream_1_U, FULL
// Channel: System_VPSS.srcImg1_data_stream_2_U, FULL
// (3): Process: System_VPSS.BGR_stream_U0
// Channel: System_VPSS.Gimage_data_stream_0_U, EMPTY
////////////////////////////////////////////////////////////////////////
// Totally 1 cycles detected!
////////////////////////////////////////////////////////////////////////
$finish called at time : 300 ns : File "D:/FPGA_Works/03_HLS_project/09_System_VPSS/solution2/sim/verilog/AESL_deadlock_report_unit.v" Line 737
## quit
INFO: [Common 17-206] Exiting xsim at Tue Jun 30 20:33:23 2020...
ERROR: [COSIM 212-303] Aborting co-simulation: RTL simulation failed.
ERROR: [COSIM 212-344] Rtl simulation failed.
ERROR: [COSIM 212-4] *** C/RTL co-simulation finished: FAIL ***
INFO: [COSIM 212-211] II is measurable only when transaction number is greater than 1 in RTL simulation. Otherwise, they will be marked as all NA. If user wants to calculate them, please make sure there are at least 2 transactions in RTL simulation.
could not read "D:/FPGA_Works/03_HLS_project/09_System_VPSS/solution2/sim/tv/rtldatafile/sim/report/cosim.log": no such file or directory
while executing
"source D:/FPGA_Works/03_HLS_project/09_System_VPSS/solution2/cosim.tcl"
invoked from within
"hls::main D:/FPGA_Works/03_HLS_project/09_System_VPSS/solution2/cosim.tcl"
("uplevel" body line 1)
invoked from within
"uplevel 1 hls::main {*}$args"
(procedure "hls_proc" line 5)
invoked from within
"hls_proc $argv"
Finished C/RTL cosimulation.

 

//====================================================================================

TOP.CPP,原文件

//====================================================================================

#include "top.h"

using namespace hls;
//================================================================================================================
void BGR_stream(GRY_IMAGE & GRYImg,RGB_IMAGE& srcImg, RGB_IMAGE& dstImg,float & Dg)
{

hls:Scalar<1,uint8_t> avg;
avg = hls::Mean<uint8_t>(GRYImg);
float Gavg = (float) avg.val[0]/255.0f;
Dg = (3.0f*Gavg*Gavg-2.0f*Gavg*Gavg*Gavg)/(2.0f*Gavg*Gavg*Gavg-3.0f*Gavg*Gavg+1.0f);

//printf("The value of Gavg is======> %f\r\n",Gavg);
//printf("The value of Dg is======> %f\r\n",Dg);

//latency_regin:{
//#pragma HLS latency min=0 max=1
for(int v=0; v<srcImg.rows; v++)
{
for(int h=0; h<srcImg.cols; h++)
{
#pragma HLS pipeline
RGB_PIXEL srcPix;
RGB_PIXEL dstPix;
srcImg >> srcPix;
dstPix.val[1] = (255.0f/(1 + Dg*((255.0f/(srcPix.val[1]))-1)*((255.0f/(srcPix.val[1]))-1)));
float G_dist = ((255.0f / (1 + Dg * ((255.0f / srcPix.val[1] - 1) * (255.0f / srcPix.val[1] - 1)))) - srcPix.val[1]);
float temp;
temp=srcPix.val[0] + G_dist;

if(temp>=255)
dstPix.val[0] = 255;
else if(temp<0)
dstPix.val[0] = 0;
else
dstPix.val[0] = temp;

temp=srcPix.val[2] + G_dist;

if(temp>=255)
dstPix.val[2] = 255;
else if(temp<0)
dstPix.val[2] = 0;
else
dstPix.val[2] = temp;

dstImg << dstPix;
}
}
// }
}

//================================================================================================================
void System_VPSS(AXI_STREAM& input_STREAM, AXI_STREAM& output_STREAM,int src_rows,int src_cols,
float & Dg)
{
#pragma HLS INTERFACE ap_none register depth=64 port=Dg
#pragma HLS INTERFACE axis port=input_STREAM
#pragma HLS INTERFACE axis port=output_STREAM
#pragma HLS INTERFACE ap_stable port=src_rows
#pragma HLS INTERFACE ap_stable port=src_cols


#pragma HLS RESOURCE core=AXI_SLAVE variable=src_rows metadata="-bus_bundle CONTROL_BUS"
#pragma HLS RESOURCE core=AXI_SLAVE variable=src_cols metadata="-bus_bundle CONTROL_BUS"
#pragma HLS RESOURCE core=AXI_SLAVE variable=return metadata="-bus_bundle CONTROL_BUS"

RGB_IMAGE srcImg (src_rows,src_cols);
RGB_IMAGE srcImg0 (src_rows,src_cols);
RGB_IMAGE srcImg1 (src_rows,src_cols);
RGB_IMAGE dstImg (src_rows,src_cols);

GRY_IMAGE Bimage (src_rows,src_cols);
GRY_IMAGE Gimage (src_rows,src_cols);
GRY_IMAGE Rimage (src_rows,src_cols);

#pragma HLS DATAFLOW

AXIvideo2Mat(input_STREAM, srcImg);
Duplicate(srcImg, srcImg0, srcImg1);
Split(srcImg0, Bimage, Gimage, Rimage);
Consume(Bimage);
Consume(Rimage);
BGR_stream(Gimage,srcImg1, dstImg,Dg);
Mat2AXIvideo(dstImg, output_STREAM);
}

 

 

 

 

//====================================================================================

联合仿真报的错误,运行的错误

//====================================================================================

****** xsim v2019.1 (64-bit)
**** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
**** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

source xsim.dir/System_VPSS/xsim_script.tcl
# xsim {System_VPSS} -autoloadwcfg -tclbatch {System_VPSS.tcl}
Vivado Simulator 2019.1
Time resolution is 1 ps
source System_VPSS.tcl
## run all
////////////////////////////////////////////////////////////////////////////////////
// Inter-Transaction Progress: Completed Transaction / Total Transaction
// Intra-Transaction Progress: Measured Latency / Latency Estimation * 100%
//
// RTL Simulation : "Inter-Transaction Progress" ["Intra-Transaction Progress"] @ "Simulation Time"
////////////////////////////////////////////////////////////////////////////////////
// RTL Simulation : 0 / 1 [n/a] @ "125000"

//////////////////////////////////////////////////////////////////////////////
// ERROR!!! DEADLOCK DETECTED at 260000 ns! SIMULATION WILL BE STOPPED! //
//////////////////////////////////////////////////////////////////////////////
/////////////////////////
// Dependence cycle 1:
// (1): Process: System_VPSS.Split_U0
// Channel: System_VPSS.srcImg0_data_stream_s_U, EMPTY
// Channel: System_VPSS.srcImg0_data_stream_1_U, EMPTY
// Channel: System_VPSS.srcImg0_data_stream_2_U, EMPTY
// (2): Process: System_VPSS.Duplicate_U0
// Channel: System_VPSS.srcImg1_data_stream_s_U, FULL
// Channel: System_VPSS.srcImg1_data_stream_1_U, FULL
// Channel: System_VPSS.srcImg1_data_stream_2_U, FULL
// (3): Process: System_VPSS.BGR_stream_U0
// Channel: System_VPSS.Gimage_data_stream_0_U, EMPTY
////////////////////////////////////////////////////////////////////////
// Totally 1 cycles detected!
////////////////////////////////////////////////////////////////////////
$finish called at time : 300 ns : File "D:/FPGA_Works/03_HLS_project/09_System_VPSS/solution2/sim/verilog/AESL_deadlock_report_unit.v" Line 737
## quit
INFO: [Common 17-206] Exiting xsim at Tue Jun 30 20:33:23 2020...
ERROR: [COSIM 212-303] Aborting co-simulation: RTL simulation failed.
ERROR: [COSIM 212-344] Rtl simulation failed.
ERROR: [COSIM 212-4] *** C/RTL co-simulation finished: FAIL ***
INFO: [COSIM 212-211] II is measurable only when transaction number is greater than 1 in RTL simulation. Otherwise, they will be marked as all NA. If user wants to calculate them, please make sure there are at least 2 transactions in RTL simulation.
could not read "D:/FPGA_Works/03_HLS_project/09_System_VPSS/solution2/sim/tv/rtldatafile/sim/report/cosim.log": no such file or directory
while executing
"source D:/FPGA_Works/03_HLS_project/09_System_VPSS/solution2/cosim.tcl"
invoked from within
"hls::main D:/FPGA_Works/03_HLS_project/09_System_VPSS/solution2/cosim.tcl"
("uplevel" body line 1)
invoked from within
"uplevel 1 hls::main {*}$args"
(procedure "hls_proc" line 5)
invoked from within
"hls_proc $argv"
Finished C/RTL cosimulation.

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Highlighted
Xilinx Employee
Xilinx Employee
365 次查看
注册日期: ‎02-28-2019

能否试一下pipeline这个指令?

-------------------------------------------------------------------------
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-------------------------------------------------------------------------
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Visitor
Visitor
356 次查看
注册日期: ‎06-30-2020

感谢你的回复!

1,将#pragma HLS dataflow 改成#pragma HLS pipeline C综合时会报以下错误,C仿真没问题,

2,没有改动时C仿真和C综合都是ok的,联合仿真才会出错,

3,对于图像处理中遍历一帧图后的值返回一个值来处理当前帧应该比较常见,例如直方图均衡化这个函数,但看了里面,并没有特别的处理的地方。

4,或者遍历前面一帧得到的均值来处理下一帧,应该如何约束呢?不通过DDR缓存帧的情况,

ERROR: [XFORM 203-733] An internal stream 'srcImg.data_stream[0].V' (09_System_VPSS/top.cpp:69) with default size is used in a non-dataflow region, which may result in deadlock. Please consider to resize the stream using the directive 'set_directive_stream' or the 'HLS stream' pragma.
ERROR: [XFORM 203-733] An internal stream 'srcImg.data_stream[1].V' (09_System_VPSS/top.cpp:69) with default size is used in a non-dataflow region, which may result in deadlock. Please consider to resize the stream using the directive 'set_directive_stream' or the 'HLS stream' pragma.
ERROR: [XFORM 203-733] An internal stream 'srcImg.data_stream[2].V' (09_System_VPSS/top.cpp:69) with default size is used in a non-dataflow region, which may result in deadlock. Please consider to resize the stream using the directive 'set_directive_stream' or the 'HLS stream' pragma.
ERROR: [XFORM 203-733] An internal stream 'srcImg0.data_stream[0].V' (09_System_VPSS/top.cpp:70) with default size is used in a non-dataflow region, which may result in deadlock. Please consider to resize the stream using the directive 'set_directive_stream' or the 'HLS stream' pragma.
ERROR: [XFORM 203-733] An internal stream 'srcImg0.data_stream[1].V' (09_System_VPSS/top.cpp:70) with default size is used in a non-dataflow region, which may result in deadlock. Please consider to resize the stream using the directive 'set_directive_stream' or the 'HLS stream' pragma.
ERROR: [XFORM 203-733] An internal stream 'srcImg0.data_stream[2].V' (09_System_VPSS/top.cpp:70) with default size is used in a non-dataflow region, which may result in deadlock. Please consider to resize the stream using the directive 'set_directive_stream' or the 'HLS stream' pragma.
ERROR: [XFORM 203-733] An internal stream 'srcImg1.data_stream[0].V' (09_System_VPSS/top.cpp:71) with default size is used in a non-dataflow region, which may result in deadlock. Please consider to resize the stream using the directive 'set_directive_stream' or the 'HLS stream' pragma.
ERROR: [XFORM 203-733] An internal stream 'srcImg1.data_stream[1].V' (09_System_VPSS/top.cpp:71) with default size is used in a non-dataflow region, which may result in deadlock. Please consider to resize the stream using the directive 'set_directive_stream' or the 'HLS stream' pragma.
ERROR: [XFORM 203-733] An internal stream 'srcImg1.data_stream[2].V' (09_System_VPSS/top.cpp:71) with default size is used in a non-dataflow region, which may result in deadlock. Please consider to resize the stream using the directive 'set_directive_stream' or the 'HLS stream' pragma.
ERROR: [XFORM 203-733] An internal stream 'dstImg.data_stream[0].V' (09_System_VPSS/top.cpp:72) with default size is used in a non-dataflow region, which may result in deadlock. Please consider to resize the stream using the directive 'set_directive_stream' or the 'HLS stream' pragma.
ERROR: [XFORM 203-733] An internal stream 'dstImg.data_stream[1].V' (09_System_VPSS/top.cpp:72) with default size is used in a non-dataflow region, which may result in deadlock. Please consider to resize the stream using the directive 'set_directive_stream' or the 'HLS stream' pragma.
ERROR: [XFORM 203-733] An internal stream 'dstImg.data_stream[2].V' (09_System_VPSS/top.cpp:72) with default size is used in a non-dataflow region, which may result in deadlock. Please consider to resize the stream using the directive 'set_directive_stream' or the 'HLS stream' pragma.
ERROR: [XFORM 203-733] An internal stream 'Bimage.data_stream[0].V' (09_System_VPSS/top.cpp:74) with default size is used in a non-dataflow region, which may result in deadlock. Please consider to resize the stream using the directive 'set_directive_stream' or the 'HLS stream' pragma.
ERROR: [XFORM 203-733] An internal stream 'Gimage.data_stream[0].V' (09_System_VPSS/top.cpp:75) with default size is used in a non-dataflow region, which may result in deadlock. Please consider to resize the stream using the directive 'set_directive_stream' or the 'HLS stream' pragma.
ERROR: [XFORM 203-733] An internal stream 'Rimage.data_stream[0].V' (09_System_VPSS/top.cpp:76) with default size is used in a non-dataflow region, which may result in deadlock. Please consider to resize the stream using the directive 'set_directive_stream' or the 'HLS stream' pragma.
ERROR: [HLS 200-70] Pre-synthesis failed.
command 'ap_source' returned error code
while executing
"source D:/FPGA_Works/03_HLS_project/09_System_VPSS/solution3/csynth.tcl"
invoked from within
"hls::main D:/FPGA_Works/03_HLS_project/09_System_VPSS/solution3/csynth.tcl"
("uplevel" body line 1)
invoked from within
"uplevel 1 hls::main {*}$args"
(procedure "hls_proc" line 5)
invoked from within
"hls_proc $argv"
Finished C synthesis.

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Xilinx Employee
Xilinx Employee
347 次查看
注册日期: ‎02-28-2019

dataflow的指令,在综合和c仿真的时候有警告信息吗?

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Visitor
Visitor
340 次查看
注册日期: ‎06-30-2020

1,综合的结果,没有用到BRAM_18K

捕获.JPG

2,以下是综合的警告信息,

2.JPG3.JPG

3,如下是联合仿真的错误信息

4.JPG

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Visitor
Visitor
334 次查看
注册日期: ‎06-30-2020

感谢你的及时回复!
使用dataflow的指令有几个警告信息,见附图,谢谢!
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Xilinx Employee
Xilinx Employee
186 次查看
注册日期: ‎02-28-2019

尝试在function中对端口添加

#pragma HLS STREAM depth = ..... variable = ......

把fifo的深度加大一点。

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Visitor
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84 次查看
注册日期: ‎06-30-2020

尝试过但还是无法解决,现在在尝试把这一个IP分成两个IP来处理,

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