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在sdsoc中产生二进制文件发上错误 ERROR: [VPL-4] Design failed to meet timing

===>The following messages were generated while Compiling (bitstream) accelerator binary: bin Log file: 
ERROR: [VPL-4] Design failed to meet timing.
Failed timing checks (paths):
{zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/Ex_V_reg_1203_reg[1]_rep/C --> zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/p_Val2_2_fu_732_p2__0/DSP_A_B_DATA_INST/B[1]}

Please check the routed checkpoint (dr_routed_timing.dcp) and timing summary report (dr_timing_summary.rpt) for more information.
ERROR: [VPL 60-704] Integration error, problem implementing dynamic region, route_design ERROR
ERROR: [VPL 60-806] Failed to finish platform linker
ERROR: [SdsCompiler 83-5019] Exiting sds++ : Error when calling '/opt/SDX/SDx/2018.2/bin/vpl --iprepo /home/workspaces/lizi/fft-vg/Debug/_sds/iprepo/repo --iprepo /opt/SDX/SDx/2018.2/data/ip/xilinx --platform /opt/SDX/SDx/2018.2/platforms/zcu102/zcu102.xpfm --temp_dir /home/workspaces/lizi/fft-vg/Debug/_sds/p0 --output_dir /home/b322/workspaces/lizi/fft-vg/Debug/_sds/p0/vpl --input_file /home/workspaces/lizi/fft-vg/Debug/_sds/p0/.xsd/top.bd.tcl --target hw --save_temps --kernels cov1:adapter --webtalk_flag SDSoC --remote_ip_cache /home/workspaces/lizi/ip_cache --xp "vivado_prop:run.impl_1.{STEPS.PHYS_OPT_DESIGN.ARGS.MORE OPTIONS}={-directive Explore}" --xp "vivado_prop:run.impl_1.{STEPS.ROUTE_DESIGN.ARGS.MORE OPTIONS}={-directive Explore}" --xp "param:compiler.deleteDefaultReportConfigs=false" '
sds++ log file saved as /home/workspaces/lizi/fft-vg/Debug/_sds/reports/sds.log
ERROR: [SdsCompiler 83-5004] Build failed

make: *** [fft-vg.elf] Error 1
makefile:45: recipe for target 'fft-vg.elf' failed

怎么解决这个问题

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回复: 在sdsoc中产生二进制文件发上错误 ERROR: [VPL-4] Design failed to meet timing

Hi, @q709505440 

可以打开Vivado工程看一下具体的timing情况。

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回复: 在sdsoc中产生二进制文件发上错误 ERROR: [VPL-4] Design failed to meet timing

Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018
| Date : Wed Jun 26 13:20:55 2019
| Host : b322 running 64-bit Ubuntu 16.04.2 LTS
| Command : report_timing_summary -slack_lesser_than 0 -file dr_timing_summary.rpt
| Design : zcu102_wrapper
| Device : xczu9eg-ffvb1156
| Speed File : -2 PRODUCTION 1.20 05-21-2018
| Temperature Grade : E
---------------------------------------------------------------------------------------------

Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : false

Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes

 

check_timing report

Table of Contents
-----------------
1. checking no_clock
2. checking constant_clock
3. checking pulse_width_clock
4. checking unconstrained_internal_endpoints
5. checking no_input_delay
6. checking no_output_delay
7. checking multiple_clock
8. checking generated_clocks
9. checking loops
10. checking partial_input_delay
11. checking partial_output_delay
12. checking latch_loops

1. checking no_clock
--------------------
There are 0 register/latch pins with no clock.


2. checking constant_clock
--------------------------
There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock
-----------------------------
There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints
--------------------------------------------
There are 0 pins that are not constrained for maximum delay.

There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay
--------------------------
There are 0 input ports with no input delay specified.

There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay
---------------------------
There are 0 ports with no output delay specified.

There are 0 ports with no output delay but user has a false path constraint

There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock
--------------------------
There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks
----------------------------
There are 0 generated clocks that are not connected to a clock source.


9. checking loops
-----------------
There are 0 combinational loops in the design.


10. checking partial_input_delay
--------------------------------
There are 0 input ports with partial input delay specified.


11. checking partial_output_delay
---------------------------------
There are 0 ports with partial output delay specified.


12. checking latch_loops
------------------------
There are 0 combinational latch loops in the design through latch input

 

------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
-1.296 -3551.138 6813 261501 0.007 0.000 0 261501 3.498 0.000 0 88469


Timing constraints are not met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock Waveform(ns) Period(ns) Frequency(MHz)
----- ------------ ---------- --------------
clk_pl_0 {0.000 5.001} 10.001 99.990
zcu102_i/clk_wiz_0/inst/clk_in1 {0.000 5.001} 10.001 99.990
clk_out2_zcu102_clk_wiz_0_0 {0.000 5.001} 10.001 99.990


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
zcu102_i/clk_wiz_0/inst/clk_in1 4.550 0.000 0 1
clk_out2_zcu102_clk_wiz_0_0 -1.296 -3551.138 6813 260637 0.007 0.000 0 260637 3.498 0.000 0 88468


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
**async_default** clk_out2_zcu102_clk_wiz_0_0 clk_out2_zcu102_clk_wiz_0_0 7.642 0.000 0 864 0.080 0.000 0 864


------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------


---------------------------------------------------------------------------------------------------
From Clock: zcu102_i/clk_wiz_0/inst/clk_in1
To Clock: zcu102_i/clk_wiz_0/inst/clk_in1

Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
PW : 0 Failing Endpoints, Worst Slack 4.550ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: zcu102_i/clk_wiz_0/inst/clk_in1
Waveform(ns): { 0.000 5.001 }
Period(ns): 10.001
Sources: { zcu102_i/clk_wiz_0/inst/clk_in1 }

Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin

 

---------------------------------------------------------------------------------------------------
From Clock: clk_out2_zcu102_clk_wiz_0_0
To Clock: clk_out2_zcu102_clk_wiz_0_0

Setup : 6813 Failing Endpoints, Worst Slack -1.296ns, Total Violation -3551.138ns
Hold : 0 Failing Endpoints, Worst Slack 0.007ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 3.498ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (VIOLATED) : -1.296ns (required time - arrival time)
Source: zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/Ex_V_reg_1203_reg[1]_rep/C
(rising edge-triggered cell FDRE clocked by clk_out2_zcu102_clk_wiz_0_0 {rise@0.000ns fall@5.001ns period=10.001ns})
Destination: zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/p_Val2_2_fu_732_p2__0/DSP_A_B_DATA_INST/B[1]
(rising edge-triggered cell DSP_A_B_DATA clocked by clk_out2_zcu102_clk_wiz_0_0 {rise@0.000ns fall@5.001ns period=10.001ns})
Path Group: clk_out2_zcu102_clk_wiz_0_0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.001ns (clk_out2_zcu102_clk_wiz_0_0 rise@10.001ns - clk_out2_zcu102_clk_wiz_0_0 rise@0.000ns)
Data Path Delay: 11.210ns (logic 3.800ns (33.898%) route 7.410ns (66.102%))
Logic Levels: 20 (CARRY8=2 DSP_A_B_DATA=1 DSP_ALU=3 DSP_M_DATA=1 DSP_MULTIPLIER=1 DSP_OUTPUT=3 DSP_PREADD_DATA=1 LUT4=4 LUT5=1 LUT6=3)
Clock Path Skew: 0.245ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 4.690ns = ( 14.691 - 10.001 )
Source Clock Delay (SCD): 3.960ns
Clock Pessimism Removal (CPR): -0.485ns
Clock Uncertainty: 0.068ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.116ns
Phase Error (PE): 0.000ns
Clock Net Delay (Source): 2.309ns (routing 0.920ns, distribution 1.389ns)
Clock Net Delay (Destination): 2.475ns (routing 0.841ns, distribution 1.634ns)

Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_out2_zcu102_clk_wiz_0_0 rise edge)
0.000 0.000 r
BUFG_PS_X0Y48 BUFG_PS 0.000 0.000 r zcu102_i/ps_e/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
net (fo=1, routed) 1.500 1.500 zcu102_i/clk_wiz_0/inst/clk_in1
MMCM_X0Y3 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1)
-0.127 1.373 r zcu102_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1
net (fo=1, routed) 0.250 1.623 zcu102_i/clk_wiz_0/inst/clk_out2_zcu102_clk_wiz_0_0
BUFGCE_X0Y74 BUFGCE (Prop_BUFCE_BUFGCE_I_O)
0.028 1.651 r zcu102_i/clk_wiz_0/inst/clkout2_buf/O
X1Y3 (CLOCK_ROOT) net (fo=99562, routed) 2.309 3.960 zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/ap_clk
SLICE_X51Y228 FDRE r zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/Ex_V_reg_1203_reg[1]_rep/C
------------------------------------------------------------------- -------------------
SLICE_X51Y228 FDRE (Prop_GFF_SLICEL_C_Q)
0.079 4.039 f zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/Ex_V_reg_1203_reg[1]_rep/Q
net (fo=121, routed) 0.345 4.384 zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/Ex_V_reg_1203_reg[1]_rep_n_15
SLICE_X51Y214 LUT4 (Prop_A6LUT_SLICEL_I2_O)
0.050 4.434 r zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/r_V_reg_1327[7]_i_2__4/O
net (fo=5, routed) 0.093 4.527 zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/r_V_reg_1327[7]_i_2__4_n_15
SLICE_X52Y213 LUT4 (Prop_G6LUT_SLICEM_I1_O)
0.037 4.564 r zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/i___273_i_3__1/O
net (fo=169, routed) 0.494 5.058 zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/i___273_i_3__1_n_15
SLICE_X54Y204 LUT4 (Prop_H6LUT_SLICEL_I2_O)
0.051 5.109 r zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/p_Val2_1_fu_709_p2_i_78__8/O
net (fo=1, routed) 0.703 5.812 zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/p_Val2_1_fu_709_p2_i_78__8_n_15
SLICE_X56Y176 LUT6 (Prop_A6LUT_SLICEM_I5_O)
0.090 5.902 r zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/p_Val2_1_fu_709_p2_i_56__8/O
net (fo=2, routed) 0.369 6.271 zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/p_Val2_1_fu_709_p2_i_56__8_n_15
SLICE_X56Y156 LUT6 (Prop_A6LUT_SLICEM_I5_O)
0.150 6.421 r zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/p_Val2_1_fu_709_p2_i_36__8/O
net (fo=2, routed) 0.050 6.471 zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/p_Val2_1_fu_709_p2_i_36__8_n_15
SLICE_X56Y156 LUT5 (Prop_B6LUT_SLICEM_I0_O)
0.089 6.560 r zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/p_Val2_1_fu_709_p2_i_18__8/O
net (fo=2, routed) 0.255 6.815 zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/p_Val2_1_fu_709_p2_i_18__8_n_15
SLICE_X58Y151 LUT6 (Prop_H6LUT_SLICEM_I2_O)
0.101 6.916 f zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/p_Val2_1_fu_709_p2_i_2__8/O
net (fo=12, routed) 1.489 8.405 zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/p_Val2_16_fu_603_p2/A[8]
DSP48E2_X12Y9 DSP_A_B_DATA (Prop_DSP_A_B_DATA_DSP48E2_A[8]_A2_DATA[8])
0.192 8.597 r zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/p_Val2_16_fu_603_p2/DSP_A_B_DATA_INST/A2_DATA[8]
net (fo=1, routed) 0.000 8.597 zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/p_Val2_16_fu_603_p2/DSP_A_B_DATA.A2_DATA<8>
DSP48E2_X12Y9 DSP_PREADD_DATA (Prop_DSP_PREADD_DATA_DSP48E2_A2_DATA[8]_A2A1[8])
0.076 8.673 r zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/p_Val2_16_fu_603_p2/DSP_PREADD_DATA_INST/A2A1[8]
net (fo=1, routed) 0.000 8.673 zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/p_Val2_16_fu_603_p2/DSP_PREADD_DATA.A2A1<8>
DSP48E2_X12Y9 DSP_MULTIPLIER (Prop_DSP_MULTIPLIER_DSP48E2_A2A1[8]_U[29])
0.505 9.178 f zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/p_Val2_16_fu_603_p2/DSP_MULTIPLIER_INST/U[29]
net (fo=1, routed) 0.000 9.178 zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/p_Val2_16_fu_603_p2/DSP_MULTIPLIER.U<29>
DSP48E2_X12Y9 DSP_M_DATA (Prop_DSP_M_DATA_DSP48E2_U[29]_U_DATA[29])
0.047 9.225 r zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/p_Val2_16_fu_603_p2/DSP_M_DATA_INST/U_DATA[29]
net (fo=1, routed) 0.000 9.225 zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/p_Val2_16_fu_603_p2/DSP_M_DATA.U_DATA<29>
DSP48E2_X12Y9 DSP_ALU (Prop_DSP_ALU_DSP48E2_U_DATA[29]_ALU_OUT[47])
0.585 9.810 f zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/p_Val2_16_fu_603_p2/DSP_ALU_INST/ALU_OUT[47]
net (fo=1, routed) 0.000 9.810 zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/p_Val2_16_fu_603_p2/DSP_ALU.ALU_OUT<47>
DSP48E2_X12Y9 DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_ALU_OUT[47]_PCOUT[47])
0.122 9.932 r zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/p_Val2_16_fu_603_p2/DSP_OUTPUT_INST/PCOUT[47]
net (fo=1, routed) 0.038 9.970 zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/p_Val2_16_fu_603_p2__0/PCIN[47]
DSP48E2_X12Y10 DSP_ALU (Prop_DSP_ALU_DSP48E2_PCIN[47]_ALU_OUT[47])
0.546 10.516 f zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/p_Val2_16_fu_603_p2__0/DSP_ALU_INST/ALU_OUT[47]
net (fo=1, routed) 0.000 10.516 zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/p_Val2_16_fu_603_p2__0/DSP_ALU.ALU_OUT<47>
DSP48E2_X12Y10 DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_ALU_OUT[47]_PCOUT[47])
0.122 10.638 r zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/p_Val2_16_fu_603_p2__0/DSP_OUTPUT_INST/PCOUT[47]
net (fo=1, routed) 0.014 10.652 zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/p_Val2_16_fu_603_p2__1/PCIN[47]
DSP48E2_X12Y11 DSP_ALU (Prop_DSP_ALU_DSP48E2_PCIN[47]_ALU_OUT[3])
0.546 11.198 f zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/p_Val2_16_fu_603_p2__1/DSP_ALU_INST/ALU_OUT[3]
net (fo=1, routed) 0.000 11.198 zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/p_Val2_16_fu_603_p2__1/DSP_ALU.ALU_OUT<3>
DSP48E2_X12Y11 DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_ALU_OUT[3]_P[3])
0.109 11.307 r zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/p_Val2_16_fu_603_p2__1/DSP_OUTPUT_INST/P[3]
net (fo=5, routed) 0.621 11.928 zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/p_Val2_16_fu_603_p2__1_n_117
SLICE_X60Y68 LUT4 (Prop_H6LUT_SLICEL_I0_O)
0.090 12.018 r zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/i___199/O
net (fo=1, routed) 0.476 12.494 zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/i___199_n_15
SLICE_X60Y94 CARRY8 (Prop_CARRY8_SLICEL_DI[0]_CO[7])
0.131 12.625 r zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/p_Val2_18_fu_658_p2_i_4__8/CO[7]
net (fo=1, routed) 0.026 12.651 zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/p_Val2_18_fu_658_p2_i_4__8_n_15
SLICE_X60Y95 CARRY8 (Prop_CARRY8_SLICEL_CI_O[3])
0.082 12.733 r zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/p_Val2_18_fu_658_p2_i_3__8/O[3]
net (fo=11, routed) 2.437 15.170 zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/p_Val2_2_fu_732_p2__0/B[1]
DSP48E2_X11Y135 DSP_A_B_DATA r zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/p_Val2_2_fu_732_p2__0/DSP_A_B_DATA_INST/B[1]
------------------------------------------------------------------- -------------------

(clock clk_out2_zcu102_clk_wiz_0_0 rise edge)
10.001 10.001 r
BUFG_PS_X0Y48 BUFG_PS 0.000 10.001 r zcu102_i/ps_e/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
net (fo=1, routed) 1.342 11.343 zcu102_i/clk_wiz_0/inst/clk_in1
MMCM_X0Y3 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT1)
0.630 11.973 r zcu102_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1
net (fo=1, routed) 0.219 12.192 zcu102_i/clk_wiz_0/inst/clk_out2_zcu102_clk_wiz_0_0
BUFGCE_X0Y74 BUFGCE (Prop_BUFCE_BUFGCE_I_O)
0.024 12.216 r zcu102_i/clk_wiz_0/inst/clkout2_buf/O
X1Y3 (CLOCK_ROOT) net (fo=99562, routed) 2.475 14.691 zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/p_Val2_2_fu_732_p2__0/CLK
DSP48E2_X11Y135 DSP_A_B_DATA r zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/p_Val2_2_fu_732_p2__0/DSP_A_B_DATA_INST/CLK
clock pessimism -0.485 14.206
clock uncertainty -0.068 14.138
DSP48E2_X11Y135 DSP_A_B_DATA (Setup_DSP_A_B_DATA_DSP48E2_CLK_B[1])
-0.264 13.874 zcu102_i/cov1_1/inst/grp_ifft_fu_387/grp_ifft_2d_two_fu_332/grp_fft_fu_194/fft_stage102_U0/grp_sin_or_cos_double_s_fu_178/p_Val2_2_fu_732_p2__0/DSP_A_B_DATA_INST
-------------------------------------------------------------------
required time 13.874
arrival time -15.170
-------------------------------------------------------------------
slack -1.296

 

 

Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: clk_out2_zcu102_clk_wiz_0_0
Waveform(ns): { 0.000 5.001 }
Period(ns): 10.001
Sources: { zcu102_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1 }

Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin

 

---------------------------------------------------------------------------------------------------
Path Group: **async_default**
From Clock: clk_out2_zcu102_clk_wiz_0_0
To Clock: clk_out2_zcu102_clk_wiz_0_0

Setup : 0 Failing Endpoints, Worst Slack 7.642ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.080ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------

 

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注册日期: ‎11-05-2018

回复: 在sdsoc中产生二进制文件发上错误 ERROR: [VPL-4] Design failed to meet timing

这上面是我的timing报告   我改怎么解决这么错误呢

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注册日期: ‎11-05-2018

回复: 在sdsoc中产生二进制文件发上错误 ERROR: [VPL-4] Design failed to meet timing

@weiyil 上面是我的报告

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