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Suarez9
Newbie
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213 次查看
注册日期: ‎12-01-2020

[Synth 8-439] module '' not found 综合基于HLS的IP失败

我在HLS中生成ip核放入vivado的BD中综合失败。

 

提示:[Synth 8-439] module 'Resize' not found ["d:/WORK/HLS_project/colorbar_hls/axi_2017_4_2/design_1/ipshared/fedc/hdl/verilog/Resize.v":254]

[Synth 8-285] failed synthesizing module 'resize' ["d:/WORK/HLS_project/colorbar_hls/axi_2017_4_2/design_1/ipshared/fedc/hdl/verilog/Resize.v":12]

[Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details

 

我参考了下述帖子:

https://forums.xilinx.com/t5/Vivado/Synth-8-439-module-not-found-%E7%BB%BC%E5%90%88%E5%9F%BA%E4%BA%8EHLS%E7%9A%84IP%E5%A4%B1%E8%B4%A5/td-p/1031081

https://www.xilinx.com/support/answers/70400.html

我尝试了在vivado Tcl 界面使用foreach ip_in_proj [get_ips] {compile_c [get_ips $ip_in_proj]},但无效,综合仍报错。怎么办?请求帮助。谢谢

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yangc
Xilinx Employee
Xilinx Employee
149 次查看
注册日期: ‎02-28-2019

是使用的non-project模式吗?在HLS综合后输出的文件中有包含该module吗?如果确认了HLS生成了该module,有没有对BD generate block design,然后找一下该module是否生成。建议一步一步定位。

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