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Explorer
Explorer
820 Views
Registered: ‎05-21-2017

Any 200MHz working example?

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Hello,

 

I'm trying to implement the "mmult" sdsoc example on the zc702 board using 200MHz for the design and 100 or 200MHz for the data motion network clock freq. In short:

A. mmult design @ 200MHz + data motion network @ 200MHz

B. mmult design @ 200MHz + data motion network @ 100MHz

 

Both implementations fail, with the performance estimation being promising:

+ Timing (ns):
    * Summary:
    +--------+-------+----------+------------+
    |  Clock | Target| Estimated| Uncertainty|
    +--------+-------+----------+------------+
    |ap_clk  |   5.00|      3.71|        1.35|
    +--------+-------+----------+------------+

 

So, the first question is:

Is this

a) a limitation introduced by SDSoC?

b) a hardware limitation of the specific board (zc702)?

c) a limitation of the AXIDMA_SIMPLE ip?

 

The second question is:

Is there any SDSoC example showing that it is possible to implement a 200MHz design using the SDSoC?

 

 

Thank you for your time,

cheers,

Panos

Without proper software tools the hardware is unusable no matter how good and well designed it is.
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Explorer
Explorer
860 Views
Registered: ‎09-19-2017

Re: Any 200MHz working example?

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Hi pmousoul

The zc702 board uses 7020 device. This device has Artix fabric which is lower performance than the Kintex fabric. Try creating a new project targeting the zc706 board and see if the build completes successfully.

The DMA and other system support IPs are hand coded HDL and should be able to achieve high freq, by far the slowest IPs in your system will be the HLS generates accelerators.

Sam
4 Replies
789 Views
Registered: ‎10-17-2017

Re: Any 200MHz working example?

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What error do you get ? 

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Explorer
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Registered: ‎05-21-2017

Re: Any 200MHz working example?

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@khareashish_trimble

 

The general error is a "Design failed to meet timing".

 

Taking as an example the "A" design described in my previous post.

 

I think that the detailed info relies in the "Release->_sds->p0->_vpl->ipi->ipiimpl->ipiimpl.runs->impl_1->dr_timming_summary.rpt" file which I attach bellow.

This file indicates that:

------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
     -1.442     -133.878                    443                32637        0.014        0.000                      0                32637        1.116        0.000                       0                 12766  


Timing constraints are not met.

and in more detail:

------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------


---------------------------------------------------------------------------------------------------
From Clock:  clk_fpga_3
  To Clock:  clk_fpga_3

Setup :          443  Failing Endpoints,  Worst Slack       -1.442ns,  Total Violation     -133.878ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.014ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        1.116ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (VIOLATED) :        -1.442ns  (required time - arrival time)
  Source:                 zc702_i/dm_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_cntr_dup_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_fpga_3  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            zc702_i/dm_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_eq_0_reg/D
                            (rising edge-triggered cell FDRE clocked by clk_fpga_3  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_fpga_3
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_fpga_3 rise@5.000ns - clk_fpga_3 rise@0.000ns)
  Data Path Delay:        6.336ns  (logic 3.178ns (50.156%)  route 3.158ns (49.844%))
  Logic Levels:           12  (CARRY4=7 LUT4=3 LUT6=2)
  Clock Path Skew:        -0.052ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.726ns = ( 7.726 - 5.000 ) 
    Source Clock Delay      (SCD):    3.008ns
    Clock Pessimism Removal (CPR):    0.230ns
  Clock Uncertainty:      0.083ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.150ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_fpga_3 rise edge)
                                                      0.000     0.000 r  
    PS7_X0Y0             PS7                          0.000     0.000 r  zc702_i/ps7/inst/PS7_i/FCLKCLK[3]
                         net (fo=1, routed)           1.193     1.193    zc702_i/ps7/inst/FCLK_CLK_unbuffered[3]
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     1.294 r  zc702_i/ps7/inst/buffer_fclk_clk_3.FCLK_CLK_3_BUFG/O
                         net (fo=12768, routed)       1.714     3.008    zc702_i/dm_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/m_axi_s2mm_aclk
    SLICE_X54Y28         FDRE                                         r  zc702_i/dm_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_cntr_dup_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X54Y28         FDRE (Prop_fdre_C_Q)         0.518     3.526 r  zc702_i/dm_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_cntr_dup_reg[3]/Q
                         net (fo=4, routed)           0.665     4.191    zc702_i/dm_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/SLICE_INSERTION/out[3]
    SLICE_X54Y28         LUT4 (Prop_lut4_I0_O)        0.124     4.315 r  zc702_i/dm_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/SLICE_INSERTION/sig_btt_lteq_max_first_incr0_carry_i_5/O
                         net (fo=1, routed)           0.000     4.315    zc702_i/dm_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/SLICE_INSERTION_n_4
    SLICE_X54Y28         CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.533     4.848 r  zc702_i/dm_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_lteq_max_first_incr0_carry/CO[3]
                         net (fo=1, routed)           0.000     4.848    zc702_i/dm_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_lteq_max_first_incr0_carry_n_0
    SLICE_X54Y29         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     4.965 r  zc702_i/dm_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_lteq_max_first_incr0_carry__0/CO[3]
                         net (fo=1, routed)           0.000     4.965    zc702_i/dm_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_lteq_max_first_incr0_carry__0_n_0
    SLICE_X54Y30         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     5.082 r  zc702_i/dm_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_lteq_max_first_incr0_carry__1/CO[3]
                         net (fo=31, routed)          0.964     6.046    zc702_i/dm_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_lteq_max_first_incr
    SLICE_X55Y29         LUT4 (Prop_lut4_I2_O)        0.124     6.170 r  zc702_i/dm_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_cntr_prv0_carry_i_3/O
                         net (fo=1, routed)           0.000     6.170    zc702_i/dm_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_cntr_prv0_carry_i_3_n_0
    SLICE_X55Y29         CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.550     6.720 r  zc702_i/dm_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_cntr_prv0_carry/CO[3]
                         net (fo=1, routed)           0.000     6.720    zc702_i/dm_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_cntr_prv0_carry_n_0
    SLICE_X55Y30         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     6.834 r  zc702_i/dm_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_cntr_prv0_carry__0/CO[3]
                         net (fo=1, routed)           0.000     6.834    zc702_i/dm_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_cntr_prv0_carry__0_n_0
    SLICE_X55Y31         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     6.948 r  zc702_i/dm_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_cntr_prv0_carry__1/CO[3]
                         net (fo=1, routed)           0.000     6.948    zc702_i/dm_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_cntr_prv0_carry__1_n_0
    SLICE_X55Y32         CARRY4 (Prop_carry4_CI_O[3])
                                                      0.313     7.261 f  zc702_i/dm_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_cntr_prv0_carry__2/O[3]
                         net (fo=1, routed)           0.309     7.570    zc702_i/dm_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_cntr_prv0[15]
    SLICE_X59Y32         LUT4 (Prop_lut4_I3_O)        0.306     7.876 f  zc702_i/dm_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_cntr[15]_i_1__0/O
                         net (fo=3, routed)           0.819     8.695    zc702_i/dm_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sel0[15]
    SLICE_X56Y32         LUT6 (Prop_lut6_I0_O)        0.124     8.819 f  zc702_i/dm_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_eq_0_i_4/O
                         net (fo=1, routed)           0.401     9.220    zc702_i/dm_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/SLICE_INSERTION/sig_sm_ld_dre_cmd_reg_1
    SLICE_X57Y33         LUT6 (Prop_lut6_I3_O)        0.124     9.344 r  zc702_i/dm_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/SLICE_INSERTION/sig_btt_eq_0_i_1/O
                         net (fo=1, routed)           0.000     9.344    zc702_i/dm_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/SLICE_INSERTION_n_16
    SLICE_X57Y33         FDRE                                         r  zc702_i/dm_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_eq_0_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_fpga_3 rise edge)
                                                      5.000     5.000 r  
    PS7_X0Y0             PS7                          0.000     5.000 r  zc702_i/ps7/inst/PS7_i/FCLKCLK[3]
                         net (fo=1, routed)           1.088     6.088    zc702_i/ps7/inst/FCLK_CLK_unbuffered[3]
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     6.179 r  zc702_i/ps7/inst/buffer_fclk_clk_3.FCLK_CLK_3_BUFG/O
                         net (fo=12768, routed)       1.547     7.727    zc702_i/dm_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/m_axi_s2mm_aclk
    SLICE_X57Y33         FDRE                                         r  zc702_i/dm_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_eq_0_reg/C
                         clock pessimism              0.230     7.956    
                         clock uncertainty           -0.083     7.873    
    SLICE_X57Y33         FDRE (Setup_fdre_C_D)        0.029     7.902    zc702_i/dm_2/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_eq_0_reg
  -------------------------------------------------------------------
                         required time                          7.902    
                         arrival time                          -9.344    
  -------------------------------------------------------------------
                         slack                                 -1.442

 

Maybe the problem is that the data mover does not support a 200MHz clock?

 

Cheers,

Panos

Without proper software tools the hardware is unusable no matter how good and well designed it is.
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Highlighted
Explorer
Explorer
861 Views
Registered: ‎09-19-2017

Re: Any 200MHz working example?

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Hi pmousoul

The zc702 board uses 7020 device. This device has Artix fabric which is lower performance than the Kintex fabric. Try creating a new project targeting the zc706 board and see if the build completes successfully.

The DMA and other system support IPs are hand coded HDL and should be able to achieve high freq, by far the slowest IPs in your system will be the HLS generates accelerators.

Sam
Explorer
Explorer
675 Views
Registered: ‎05-21-2017

Re: Any 200MHz working example?

Jump to solution

 

Thank you Sam,

 

I tested what you said and you are right.

 

So, in short the answer is:

b) a hardware limitation of the specific board (zc702)

 

 

Cheers,

Panos

Without proper software tools the hardware is unusable no matter how good and well designed it is.
0 Kudos