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Visitor pro711
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Registered: ‎03-26-2018

C-Callable IP with master AXI ports

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Hello,

 

I have a custom RTL IP that I would like to package as a C-Callable IP in SDSoC. The IP has a slave AXI-Lite port for control and a master AXI port for memory accesses. From the documentation, if the master port is mapped to an argument of the C function, then the "-map" option can be passed to sdx_pack to connect the master AXI port to the rest of the system:

 

For example, if we have:

 

void foo(int* array) {}

 

Then we can pass the following option to sdx_pack:

 

​-map array=s_axilite:in:0x18,m_axi:inout

 

However, in my case, the master AXI port is not mapped to one of the C arguments. Instead, the IP generates the read/write addresses internally. Thus, the "-map" option does not apply here. The resulting problem is that SDSoC leaves the master AXI port unconnected. Is there another way to specify that the AXI port needs to be connected in the SDSoC flow? Thanks.

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Explorer
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Registered: ‎09-19-2017

Re: C-Callable IP with master AXI ports

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Hi pro711,

 

SDSoC's concept of hardware requires a mapping from a function and its arguments to an accelerator and its ports. If you have an AXI-Master port on an accelerator, what is its significance to the functionality of the accelerator? Can you find an appropriate mapping to a function argument? Also, SDSoC supports an abstraction around accelerators and their data such that accelerators must be told where their data lives (ie. via an address). This is necessary since arrays are gennerally allocated and there is no guarantee that an array will always live at a particular address in memory.  

 

Can you describe more about your system and how your accelerator works (control, data access, etc.)? What is your AXI-Master port connected to and where will it be reading/writing from (DDR?).

 

Sam

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Explorer
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Registered: ‎09-19-2017

Re: C-Callable IP with master AXI ports

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Hi pro711,

 

SDSoC's concept of hardware requires a mapping from a function and its arguments to an accelerator and its ports. If you have an AXI-Master port on an accelerator, what is its significance to the functionality of the accelerator? Can you find an appropriate mapping to a function argument? Also, SDSoC supports an abstraction around accelerators and their data such that accelerators must be told where their data lives (ie. via an address). This is necessary since arrays are gennerally allocated and there is no guarantee that an array will always live at a particular address in memory.  

 

Can you describe more about your system and how your accelerator works (control, data access, etc.)? What is your AXI-Master port connected to and where will it be reading/writing from (DDR?).

 

Sam

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Visitor pro711
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Registered: ‎03-26-2018

Re: C-Callable IP with master AXI ports

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Hi Sam,

 

Thanks for your answer. My accelerator works by receiving some arguments from the AXI-Lite control interface and then accesses the DDR (via ACP/HP ports) on its master AXI ports. The memory addresses are computed based on the arguments. I managed to make one of the arguments a pointer, and was able to use the "-map" directive now.

 

Another question I have is that I am designing an accelerator IP with multiple PEs / multiple master AXI ports. The accelerator receives input data as a single pointer to an array, and internally partitions the array and distributes the chunks to the PEs for processing. I wanted to reuse the approach above for packaging the accelerator as a C-Callable IP, but because I am passing in a single array, I can only bind it to one of the AXI ports. The other AXI ports are still unconnected. One workaround I thought about is to have multiple pointer arguments in the C function signature, and bind them to different AXI ports. But this seems a little redundant, as all the pointers will receive the same value. Is there a better way to achieve the same goal?

 

Tao

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Explorer
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Registered: ‎09-19-2017

Re: C-Callable IP with master AXI ports

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Hi Tao,

Glad to hear your making progress with sdx_pack. Unfortunately, SDSoC still has a hardware centric view of function-to-accelerator mapping. There is no way (currently) to bind multiple hardware ports to a single argument on the function. So you will need to have a separate argument for each M_AXI port. But you should be able to re-use the same control offset in the S_AXI register map.

Once SDSoC supports argument optimization at the function-level (ie. partitioning, mapping, reshape) then it will need to support many ports mapping to a single argument. So the feature should come eventually

Sam

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Visitor pro711
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Registered: ‎03-26-2018

Re: C-Callable IP with master AXI ports

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Hi Sam,

 

Thanks! Another quick question, is there a way to specify the clock frequency the C-Callable IP runs at? I know that for SDSoC-generated hardware the "-clkid" option can be used, but I did not find a way to do that for C-Callable RTL IPs.

 

Tao

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Registered: ‎09-19-2017

Re: C-Callable IP with master AXI ports

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Hi Tao,

C-Callable IPs fall into the "C-Callable Library" category. When you use a C-Callable library you do not specify the accelerator on the command line like you do with C/HLS functions (as you pointed out). There is no way (as far as I know) in 2017.4 that user's can specify the clock frequency for C-Callable IPs from a library.

What that means is that C-Callable IPs will be connected to the "Data Motion Network Clock" which can be set with -dmclkid flag from the command line. But keep in mind that this clock net is connected to all of your data mover IPs (AXI IC, DMAs, etc.) so it cannot be run too high.

Hopefully there will be a feature in the future for setting the clock individually for C-Callable IPs.

Sam
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Registered: ‎09-19-2017

Re: C-Callable IP with master AXI ports

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Update,

Looks like C-Callable IPs are set to the "Platform default clock ID", not the DM clock ID. Meaning that the clock is not user-configurable.

So if you dont like the platform default clock ID, you would have to rebuild the platform (UG1146) with a different default clock.

Hopefully this will be fixed in a future release.

Sam
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Visitor pro711
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Registered: ‎03-26-2018

Re: C-Callable IP with master AXI ports

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Hi Sam,

 

Thanks for the clarification. I will look into that.

 

Just as one data point, it seems "-dmclkid" did change the C-Callable IP clock in my case (from looking at the IP integrator block diagram). I am using SDSoC 2017.2.

 

Tao

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