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Visitor
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Registered: ‎12-13-2018

Could not place shape in pblock pblock_dynamic_SLR1

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Hi. I was wondering if someone has encountered similar problems. I was using Vitis 2019.2 with RTL kernel. Without manual guidance on SLR partitioning, it routes at a very low frequency (~115MHz), which underutilizes the memory bandwidth. Since the critical path is related to SLR crossing, on U250 board I was able to improve timing by manually assigning some modules to SLRs, using the method mentioned in https://forums.aws.amazon.com/message.jspa?messageID=902420. More specifically, I created a file with something like

add_cells_to_pblock [get_pblocks pblock_dynamic_SLR1] [get_cells -hierarchical -regex {
(.*/)?fifos/inst\\[1]\\.unit
}
add_cells_to_pblock [get_pblocks pblock_dynamic_SLR0] [get_cells -hierarchical -regex {
(.*/)?fifos/inst\\[2]\\.unit
}

and added the following to the v++ command:

--vivado.prop run.impl_1.STEPS.OPT_DESIGN.TCL.PRE=xxx.tcl

This worked well on U250 but failed when I migrate to U280 with the following error:

ERROR: [Place 30-642] Placement Validity Check : Failed to find legal placement.
Reason: Could not place shape in pblock pblock_dynamic_SLR1.
The unplaced cells are: 
  Cell pfm_top_i/dynamic_region/top/inst/fifos/inst[1].unit/srl.unit/out_ptr[0]_i_1 of type LUT1
  Cell pfm_top_i/dynamic_region/top/inst/fifos/inst[1].unit/srl.unit/if_dout[0]_INST_0 of type LUT4
  Cell pfm_top_i/dynamic_region/top/inst/fifos/inst[1].unit/srl.unit/out_ptr_reg[0] of type FDSE
  Cell pfm_top_i/dynamic_region/top/inst/fifos/inst[2].unit/srl.unit/mem_reg[0][0] of type FDRE
Shape dimensions: Width = 1, Height = 1
The unplaced cells have different pblocks. Here are the cells with pblocks:
Cell pfm_top_i/dynamic_region/top/inst/fifos/inst[1].unit/srl.unit/out_ptr[0]_i_1 has pblock pblock_dynamic_SLR1
Cell pfm_top_i/dynamic_region/top/inst/fifos/inst[1].unit/srl.unit/if_dout[0]_INST_0 has pblock pblock_dynamic_SLR1
Cell pfm_top_i/dynamic_region/top/inst/fifos/inst[1].unit/srl.unit/out_ptr_reg[0] has pblock pblock_dynamic_SLR1
Cell pfm_top_i/dynamic_region/top/inst/fifos/inst[2].unit/srl.unit/mem_reg[0][0] has pblock pblock_dynamic_SLR0

With some Googling I found this post, suggesting this could be caused by the synthesizer putting the cells from two pblocks in the same inseparable unit and suggests that the solution is "to override the pblock assignments for individual cells". However, I am not sure how it could be done. What I have tried so far is that I put (* dont_touch = "yes" *) pragmas on the wires connecting inst[1].unit and inst[2].unit and the module instantiations of inst[1].unit and inst[2].unit, which I assume would let the synthesizer not to put the cells together. It did not solve the problem. I was wondering if there are other explanations and/or solutions to this problem.

Thanks.

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Moderator
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Registered: ‎11-04-2010

Re: Could not place shape in pblock pblock_dynamic_SLR1

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Hi, @blaok ,

In your schematic, I can see the cross-slr path is LUT-> FF.

Please change the structure to FF->FF and try again.

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cross_slr.png
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Moderator
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Registered: ‎11-04-2010

Re: Could not place shape in pblock pblock_dynamic_SLR1

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Hi, @blaok ,

Could you show me the schematic connection of the FF in SLR0 with the other cell in SLR1?

Could you also try the other place directives based on the opt_design?

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Re: Could not place shape in pblock pblock_dynamic_SLR1

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Hi @hongh,

Thanks for your reply. Apologies for making the post lengthy; I am not sure which part can be safely omitted and decided to post the whole module. Basically, I am connecting N FWFT FIFOs directly such that any element written into the FIFO can be read after N cycles:

 

module fifos #(
    parameter DATA_WIDTH = 32,
    parameter ADDR_WIDTH = 5,
    parameter DEPTH      = 2,
    parameter LEVEL      = 2
) (
  input wire clk,
  input wire reset,

  // write
  output wire                  if_full_n,
  input  wire                  if_write_ce,
  input  wire                  if_write,
  input  wire [DATA_WIDTH-1:0] if_din,

  // read
  output wire                  if_empty_n,
  input  wire                  if_read_ce,
  input  wire                  if_read,
  output wire [DATA_WIDTH-1:0] if_dout
);

  (* dont_touch = "yes" *) wire                  full_n  [LEVEL:0];
  (* dont_touch = "yes" *) wire                  empty_n [LEVEL:0];
  (* dont_touch = "yes" *) wire [DATA_WIDTH-1:0] data    [LEVEL:0];

  localparam kDepthPerUnit = (DEPTH - 1) / LEVEL + 1;

  genvar i;
  for (i = 0; i < LEVEL; i = i + 1) begin : inst
    fifo #(
      .DATA_WIDTH(DATA_WIDTH),
      .ADDR_WIDTH(ADDR_WIDTH),
      .DEPTH(kDepthPerUnit < 2 ? 2 : kDepthPerUnit)
    ) unit (
      .clk(clk),
      .reset(reset),

      // connect to fifo[i+1]
      .if_empty_n(empty_n[i+1]),
      .if_read_ce(if_read_ce),
      .if_read   (full_n[i+1]),
      .if_dout   (data[i+1]),

      // connect to fifo[i-1]
      .if_full_n  (full_n[i]),
      .if_write_ce(if_write_ce),
      .if_write   (empty_n[i]),
      .if_din     (data[i])
    );
  end

  // write
  assign if_full_n  = full_n[0];  // output
  assign empty_n[0] = if_write;   // input
  assign data[0]    = if_din;     // input

  // read
  assign if_empty_n    = empty_n[LEVEL];  // output
  assign full_n[LEVEL] = if_read;         // input
  assign if_dout       = data[LEVEL];     // output

endmodule   // fifos

 

Parameters used are

.DATA_WIDTH(33),
.ADDR_WIDTH(1),
.DEPTH(2),
.LEVEL(3)

The if_read_ce and if_write_ce signals bind to constant 1 when instantiating, and I was expecting each child FIFO to be placed in one SLR and the SLR crossing only happens through the dont_touch wires. Each child fifo is an SRL FIFO:

 

module fifo_srl #(
  parameter MEM_STYLE  = "shiftreg",
  parameter DATA_WIDTH = 32,
  parameter ADDR_WIDTH = 5,
  parameter DEPTH      = 32
) (
  input wire clk,
  input wire reset,

  // write
  output wire                  if_full_n,
  input  wire                  if_write_ce,
  input  wire                  if_write,
  input  wire [DATA_WIDTH-1:0] if_din,

  // read
  output wire                  if_empty_n,
  input  wire                  if_read_ce,
  input  wire                  if_read,
  output wire [DATA_WIDTH-1:0] if_dout
);

  wire [ADDR_WIDTH - 1:0] shift_reg_addr;
  wire [DATA_WIDTH - 1:0] shift_reg_data;
  wire [DATA_WIDTH - 1:0] shift_reg_q;
  wire                    shift_reg_ce;
  reg  [ADDR_WIDTH:0]     out_ptr;
  reg                     internal_empty_n;
  reg                     internal_full_n;

  reg [DATA_WIDTH-1:0] mem [0:DEPTH-1];

  assign if_empty_n = internal_empty_n;
  assign if_full_n = internal_full_n;
  assign shift_reg_data = if_din;
  assign if_dout = shift_reg_q;

  assign shift_reg_addr = out_ptr[ADDR_WIDTH] == 1'b0 ? out_ptr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
  assign shift_reg_ce = (if_write & if_write_ce) & internal_full_n;

  assign shift_reg_q = mem[shift_reg_addr];

  always @(posedge clk) begin
    if (reset) begin
      out_ptr <= ~{ADDR_WIDTH+1{1'b0}};
      internal_empty_n <= 1'b0;
      internal_full_n <= 1'b1;
    end else begin
      if (((if_read && if_read_ce) && internal_empty_n) &&
          (!(if_write && if_write_ce) || !internal_full_n)) begin
        out_ptr <= out_ptr - 1'b1;
        if (out_ptr == {(ADDR_WIDTH+1){1'b0}})
          internal_empty_n <= 1'b0;
        internal_full_n <= 1'b1;
      end
      else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
        ((if_write & if_write_ce) == 1 & internal_full_n == 1))
      begin
        out_ptr <= out_ptr + 1'b1;
        internal_empty_n <= 1'b1;
        if (out_ptr == DEPTH - {{(ADDR_WIDTH-1){1'b0}}, 2'd2})
          internal_full_n <= 1'b0;
      end
    end
  end

  integer i;
  always @(posedge clk) begin
    if (shift_reg_ce) begin
      for (i = 0; i < DEPTH - 1; i = i + 1)
        mem[i + 1] <= mem[i];
      mem[0] <= shift_reg_data;
    end
  end

endmodule  // fifo_srl

 

Besides, could you be more specific on 


Could you also try the other place directives based on the opt_design?


I am currently using

 

    --vivado.prop=run.impl_1.STRATEGY=Performance_EarlyBlockPlacement

Are you suggesting I should try something else? This is the best strategy among the default and Congestion_SpreadLogic_high, based on my limited trial-and-errorson U250.

 

Thank you.

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Moderator
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Registered: ‎11-04-2010

Re: Could not place shape in pblock pblock_dynamic_SLR1

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Hi, @blaok ,

Please add -R2 option to save the intermediate result. 

In the generated Vivado run dir, you can see the result of opt_design: XX_opt .dcp

You can open this opt.dcp in Vivado for further debugging. Check the schematic of the reported cells or try different place strategies.

Is it possible for you to provide such opt.dcp file? 

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Registered: ‎11-04-2010

Re: Could not place shape in pblock pblock_dynamic_SLR1

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Hi, @blaok ,

In your schematic, I can see the cross-slr path is LUT-> FF.

Please change the structure to FF->FF and try again.

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-------------------------------------------------------------------------

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cross_slr.png
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Visitor
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Registered: ‎12-13-2018

Re: Could not place shape in pblock pblock_dynamic_SLR1

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Thank you! Now Vivado can run beyond the Placer Initialization phase.

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