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Participant mkaiser
Participant
2,638 Views
Registered: ‎07-24-2017

Create SDAccel DSA without partial reconfiguration

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Hi,
I am trying to get SDAccel started on our custom board, that has no PCIe endpoint. Therefore I don't need really the partial reconfiguration flow. To keep things simple I like to have for an SDAccel output only one bitstream file including the OCL infrastructure and the kernel implementations.

This is what I tried:
- The "Use Partial Reconfiguration" checkbox in the Open CL Region has been deselected. Also I tried both "Use non-PR synthesized design in DSA" checked and unchecked.
- In addition I set "set_property dsa.uses_pr false [current_project]"
- The generated DSA has been successfully validated.
- In SDAccel the following error occurs (VADD example Kernel)

 

 

ERROR: [XOCC 2-1501] Error: The specified cell 'sdaccel_en_gen.design_1_i/ocl_block_0' cannot be turned into a black box because it is not marked as reconfigurable module, and the design has routing information.
Resolution: 
1. If the cell is intended to be reconfigurable, please verify that HD.RECONFIGURABLE property is being set on the cell. 
2. If the cell is not reconfigurable, remove all routing information by 'route_design -unroute' before running this command. 
ERROR: [XOCC 60-760] In '/homes/juser/workspace/vadd/_xocc_krnl_vadd_bin_vadd_hw.dir/impl/build/system/bin_vadd_hw/bitstream/bin_vadd_hw_ipi/vivado.log', caught Tcl error: ERROR: [Common 17-39] 'update_design' failed due to earlier errors.
WARNING: [XOCC 60-732] Link warning: There is no resource utilization data in DSA, utilization DRC is skipped
ERROR: [XOCC 60-704] Integration error, problem updating DSA design
ERROR: [XOCC 60-597] Kernel build failed to complete
ERROR: [XOCC 60-702] Failed to finish compilation and linking


So for my case the 2. resolution is relevant.

My Questions are:
- When and where should the "route-design -unroute" command be issued?
- Is there in general a way to generate a single "full" bitstream via SDACcel (no PCIe, no PR)?

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Participant mkaiser
Participant
3,286 Views
Registered: ‎07-24-2017

Re: Create SDAccel DSA without partial reconfiguration

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eppur si muove...

after some digging in the underlying tcl-scripts we found the issue and we were able to fix it for our needs.

 

File:

 

%XILINX_INSTALL_DIR%/SDx/2017.2/scripts/ocl/ocl_util.tcl

function (line 2996):

proc create_bitstreams_with_run { dsa_info config_info clk_info design_name } { 

 

In line 3114 the write_bitstream parameters are set. The code only covers the flow for PR. For a non-partial flow an "else" statement needs to be added:

 

Original:

 

# pass -cell to write_bitstream to only generate the partial bit files for pr
if { $dsa_uses_pr } {
set more_option [get_property {STEPS.WRITE_BITSTREAM.ARGS.MORE OPTIONS} [get_runs impl_1]]
set_property -name {STEPS.WRITE_BITSTREAM.ARGS.MORE OPTIONS} -value "$more_option -cell $ocl_inst_path" -objects [get_runs impl_1] 
}

After:

set more_option [get_property {STEPS.WRITE_BITSTREAM.ARGS.MORE OPTIONS} [get_runs impl_1]]
# pass -cell to write_bitstream to only generate the partial bit files for pr
if { $dsa_uses_pr } {
set_property -name {STEPS.WRITE_BITSTREAM.ARGS.MORE OPTIONS} -value "$more_option -cell $ocl_inst_path" -objects [get_runs impl_1] 
} else {
set_property -name {STEPS.WRITE_BITSTREAM.ARGS.MORE OPTIONS} -value "$more_option -no_partial_bitfile" -objects [get_runs impl_1] 
}

Otherwise no bitstream arguments would be set at all. Running SDAccel with these patches (patch works for 2017.1 and 2017.2) will generate full bitstreams (works currently only for non expanded region flows)

 

I am unsure how to /where to submit this small patch. To whom should I report this issue?

3 Replies
Moderator
Moderator
2,588 Views
Registered: ‎03-27-2012

Re: Create SDAccel DSA without partial reconfiguration

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Currently PCIe is the only channel for host applications to communicate with hardware platform on SDAccel environment.

If your board doesn't have PCIe interface, then it won't work for SDAccel.

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Participant mkaiser
Participant
2,575 Views
Registered: ‎07-24-2017

Re: Create SDAccel DSA without partial reconfiguration

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Thanks for your answer,

my no "PCIe-endpoint" was somehow misleading. There is a PCIe endpoint, but not on the FPGA on the board, I want to use for SDAccel...

 

In fact I already have the SDAccel flow running, but like I said, I want to skip the partial reconfiguration on board.

 

Any ideas?

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Highlighted
Participant mkaiser
Participant
3,287 Views
Registered: ‎07-24-2017

Re: Create SDAccel DSA without partial reconfiguration

Jump to solution

eppur si muove...

after some digging in the underlying tcl-scripts we found the issue and we were able to fix it for our needs.

 

File:

 

%XILINX_INSTALL_DIR%/SDx/2017.2/scripts/ocl/ocl_util.tcl

function (line 2996):

proc create_bitstreams_with_run { dsa_info config_info clk_info design_name } { 

 

In line 3114 the write_bitstream parameters are set. The code only covers the flow for PR. For a non-partial flow an "else" statement needs to be added:

 

Original:

 

# pass -cell to write_bitstream to only generate the partial bit files for pr
if { $dsa_uses_pr } {
set more_option [get_property {STEPS.WRITE_BITSTREAM.ARGS.MORE OPTIONS} [get_runs impl_1]]
set_property -name {STEPS.WRITE_BITSTREAM.ARGS.MORE OPTIONS} -value "$more_option -cell $ocl_inst_path" -objects [get_runs impl_1] 
}

After:

set more_option [get_property {STEPS.WRITE_BITSTREAM.ARGS.MORE OPTIONS} [get_runs impl_1]]
# pass -cell to write_bitstream to only generate the partial bit files for pr
if { $dsa_uses_pr } {
set_property -name {STEPS.WRITE_BITSTREAM.ARGS.MORE OPTIONS} -value "$more_option -cell $ocl_inst_path" -objects [get_runs impl_1] 
} else {
set_property -name {STEPS.WRITE_BITSTREAM.ARGS.MORE OPTIONS} -value "$more_option -no_partial_bitfile" -objects [get_runs impl_1] 
}

Otherwise no bitstream arguments would be set at all. Running SDAccel with these patches (patch works for 2017.1 and 2017.2) will generate full bitstreams (works currently only for non expanded region flows)

 

I am unsure how to /where to submit this small patch. To whom should I report this issue?