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142 Views
Registered: ‎10-14-2019

DDR Bandwidth Calculation

We have run cpu_to_fpga/03_burstrw_c

Device: U280

Tool Version: SDAccel 2019.1

The Throughputs Reported by the Tool: (.csv file)

Host -> DDR1 (Read): 1.522 Gb/s

DDR1 -> Host (White): 3.561 Gb/s

These values seem to be very less. 

Can any on please suggest? 

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Xilinx Employee
Xilinx Employee
67 Views
Registered: ‎06-04-2018

Re: DDR Bandwidth Calculation

Hi @madhukrishna_kaza,

You can refer the host_global_bandwidth design to check the bandwidth.

https://github.com/Xilinx/Vitis_Accel_Examples/tree/master/host/host_global_bandwidth

If you are going with U280 platform, please update the bank mapping according in krnl_host_global.ini file.

Regards,
Vishnu
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