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Visitor siva_krishna
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Registered: ‎04-06-2016

ERROR: [VRFC 10-2063] Module not found while processing module instance

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When I am building a project I got this error and build terminated

 

...ERROR: [Synth 8-439] module 'hog_hw_am_submul_23ns_23ns_17s_41_1_DSP48_0' not found [e:/sdsoc_siva/complete/SDRelease/_sds/p0/ipi/zedboard_osd.srcs/sources_1/ipshared/xilinx.com/hog_hw_v1_0/139ac31a/hdl/verilog/hog_hw_am_submul_23ns_23ns_17s_41_1.v:28]
ERROR: [Synth 8-285] failed synthesizing module 'hog_hw_am_submul_23ns_23ns_17s_41_1' [e:/sdsoc_siva/complete/SDRelease/_sds/p0/ipi/zedboard_osd.srcs/sources_1/ipshared/xilinx.com/hog_hw_v1_0/139ac31a/hdl/verilog/hog_hw_am_submul_23ns_23ns_17s_41_1.v:9]
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
ERROR: [Common 17-70] Application Exception: Failed to launch run 'impl_1' due to failures in the following run(s):
ERROR: [SDSoC 0-0] Exiting system_linker: Error when calling 'vivado -mode batch -source "E:/sdsoc_siva/complete/SDRelease/_sds/p0/ipi/top.impl.tcl"'
ERROR: [SDSoC 0-0] Exiting sds++ : Error when calling 'system_linker -cf-input E:/sdsoc_siva/complete/SDRelease/_sds/.llvm/apsys_0.xml -cf-output-dir _sds/p0 -ip-db E:/sdsoc_siva/complete/SDRelease/_sds/.cdb/xd_ip_db.xml -ip-repo E:/sdsoc_siva/complete/SDRelease/_sds/iprepo/repo -sds-pf C:/Xilinx/SDSoC/2015.2.1/platforms/zedboard_osd:linux -bitstream -bit-name complete.elf.bit -boot-files -mdev-no-swgen -mdev-no-xsd -sdsoc -sd-output-dir _sds/p0/sd_card -bit-binary -elf E:/sdsoc_siva/complete/SDRelease/_sds/swstubs/complete.elf'

 

I am trying to transfer a function to PL which contains five subfunctions. Each subfunctions can run concurrently. So, I have to use dataflow pragma and make intermediate buffers as FIFO to make them run concurrently. In vivado hls I can specify dataflow option through configuration settings. But in SDSoC I have to mention it interms of pragmas, which is not possible. So, I have manually provided tcl script for synthesis. After mentioning all these I tried to build thorugh SDRelease and it terminated with the above error. However I can successfully run SDEstimate.

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Xilinx Employee
Xilinx Employee
13,956 Views
Registered: ‎06-29-2015

Re: ERROR: [VRFC 10-2063] Module not found while processing module instance

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Hi Siva,

 

When I look at the sds_hog.log in _sds/reports directory, it looks like the HLS is synthesizing the IP twice, but only packaging once. So there might be a problem with your directives.tcl script. In particular, it looks like it is doing synth, pack, synth and then the 2nd time not packed so that may be why a file is missing (and so you're getting that synthesis error).

 

So heres a couple of suggestions:

1. Upgrade to 2016.1, there have been quite a few improvements in Vivado, HLS, and SDSoC since 2015.2.1

2. The directives.tcl option is super manual, and more of a back door. We highly advise that you use pragmas in your code rather than HLS tcl commands (you can do 99.999% of everything with pragmas)

3. Convert your use of the HLS tcl commands in directives.tcl file to pragmas. Then you'll have to have a pragma for each variable that you're marking as a stream for dataflow and be able to specify different depths for each. For example: #pragma HLS stream depth=8 variable=OutStream

 

If you need help converting your directives.tcl to pragmas, feel free to post that tcl script and the relevant source code and we can work it out. If you dont want your source public, feel free to private message me the files.

 

Sam

 

 

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Xilinx Employee
Xilinx Employee
7,865 Views
Registered: ‎06-29-2015

Re: ERROR: [VRFC 10-2063] Module not found while processing module instance

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Hi Siva,

 

Can you attach this file: 

E:/sdsoc_siva/complete/SDRelease/_sds/iprepo/repo/xilinx_com_hls_hog_hw_1_0/hdl/verilog/hog_hw_am_submul_23ns_23ns_17s_41_1.v 

 

Can you also include the *.log and *.jou in E:/sdsoc_siva/complete/SDRelease/_sds/reports

 

Thanks

Sam

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Visitor siva_krishna
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Registered: ‎04-06-2016

Re: ERROR: [VRFC 10-2063] Module not found while processing module instance

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Also, is it possible to specify dataflow channel as FIFO in sdsoc directly as a pragma. Is there any way such that each channel can be of different size?.

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Xilinx Employee
Xilinx Employee
13,957 Views
Registered: ‎06-29-2015

Re: ERROR: [VRFC 10-2063] Module not found while processing module instance

Jump to solution

Hi Siva,

 

When I look at the sds_hog.log in _sds/reports directory, it looks like the HLS is synthesizing the IP twice, but only packaging once. So there might be a problem with your directives.tcl script. In particular, it looks like it is doing synth, pack, synth and then the 2nd time not packed so that may be why a file is missing (and so you're getting that synthesis error).

 

So heres a couple of suggestions:

1. Upgrade to 2016.1, there have been quite a few improvements in Vivado, HLS, and SDSoC since 2015.2.1

2. The directives.tcl option is super manual, and more of a back door. We highly advise that you use pragmas in your code rather than HLS tcl commands (you can do 99.999% of everything with pragmas)

3. Convert your use of the HLS tcl commands in directives.tcl file to pragmas. Then you'll have to have a pragma for each variable that you're marking as a stream for dataflow and be able to specify different depths for each. For example: #pragma HLS stream depth=8 variable=OutStream

 

If you need help converting your directives.tcl to pragmas, feel free to post that tcl script and the relevant source code and we can work it out. If you dont want your source public, feel free to private message me the files.

 

Sam

 

 

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Visitor siva_krishna
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7,832 Views
Registered: ‎04-06-2016

Re: ERROR: [VRFC 10-2063] Module not found while processing module instance

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Hello,

    I have converted the tcl commands to pragmas as you said. Now, it was able to synthesize wihtout custom tcl file. However when I tried to run the program it simply hangs after start. What I thought the reason may be as explained in HLS user guide the FIFO's should be large enough to prevent stalling. However blocks in my design works at different rate. I can not put the default size for FIFO's, as it is very large. Is there any way to prevent stalling?

 

In general funtion interface is implemented as ap_ctrl_hs. But, I want to implement it as ap_ctrl_none. But it is not allowing me to do this in SDSoC using pragma. It is giving error like this

 

INFO: [SDSoC 0-0] ap_ctrl_none control protocol has been specified, only axis interface allowed for all arguments!
ERROR: [SDSoC 0-0] inp interface type not supported with ap_ctrl_none control protocol!
ERROR: [SDSoC 0-0] Failed to generate interface tcl script: E:/sdsoc_siva/fifo_test/SDEstimate/_sds/vhls/hw.tcl

 

Here inp is my top module argument with fifo interface. However I am able to synthesize in HLS, but not in SDSoC. Actually we are using generated HDL files in some other design, for that reason I want to synthesize with ap_ctrl_none interface.

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Xilinx Employee
Xilinx Employee
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Registered: ‎06-29-2015

Re: ERROR: [VRFC 10-2063] Module not found while processing module instance

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Hi Siva,

 

It "hangs after start", if you debug your application and step through, where does it hang? There is a stub function that SDSoC generates that replaces your function body (of the function you marked for hardware) with commands to start the accelerator, send/recv data, etc. Can you point to which of those its hanging at?

 

You could try the trace feature in 2016.1 that inserts cores and shows you when things happen at runtime. It will show you when software starts the accelerator and starts the DMAs, and when the accelerator actually starts in hardware, when each data transfer actually starts/stops in hardware. That might give you more idea about whats going wrong.

 

Implementing functions as ap_ctrl_none is possible but not recommended for a variety of reasons. The first requriements is that all arguments into/out-of the accelerator have to be AXI-Streams. SDSoC supports only AXI memory mapped and AXI-Stream interfaces as connections between cores (and DMAs, and other assicated interconnect IPs). So if there is ap_ctrl_none on the interface, then SDSoC does not do anything to help with the interfacing (ie. fifo to AXI-Stream conversion). Its a very manual mode/setting. And you have to use only HLS interface pragmas (#pragma HLS INTERFACE ap_ctrl_none port=return) and (#pragma HLS INTERFACE axis arg_name). Everything has to be AXI-Stream, so 'axis' and not 'fifo' interfaces. In addition, you'll need to add support for the TLAST signal manually (google hls axi stream tlast). So its possible, but not quite straight forward. In addition SDSoC requires that for any AXI-Stream to AXI-Stream connection that either both interfaces have TLAST, or neither has TLAST. Remember that any data movers (AXI-FIFO, simple/SG DMA) will have TLAST. So you'll need to plan accordingly.

 

We recommend that you dont use ap_ctrl_none except in rare cases. Almost always you can do without, and it will be easier to get the design working first.

 

Sam

 

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