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Participant mkaiser
Participant
1,418 Views
Registered: ‎07-24-2017

Errors in SDAccel 2018.1 platform development reference design (UG1164)

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hi,

 

I just tried to migrate our DSA to 2018.1 using the reference design. It seems like the associated files for UG 1164 (ug1164-sdaccel-platform-development.zip, link ) have not been updated (both kintex and virtex are affected).

 

They work fine for 2017.4, but not for 2018.1.

Can you please review this?

 


from vivado.log, lines 2926 - 2958

ERROR: [IP_Flow 19-3460] Validation failed on parameter 'Const Width(CONST_WIDTH)' for "Const Value is out of range -2147483647:4294967295 allowed by width"
. BD Cell 'static_region/dma_irq_config'
ERROR: [IP_Flow 19-3460] Validation failed on parameter 'Const Val(CONST_VAL)' for Const Value is out of range -2147483647:4294967295 allowed by width
. BD Cell 'static_region/dma_irq_config'
INFO: [IP_Flow 19-3438] Customization errors found on 'static_region/dma_irq_config'. Restoring to previous valid configuration.
INFO: [Common 17-17] undo 'set_property'
ERROR: [Common 17-39] 'set_property' failed due to earlier errors.

while executing
"rdi::add_properties -dict {CONFIG.CONST_VAL 6148914689804861440 CONFIG.CONST_WIDTH 32} /static_region/dma_irq_config"
invoked from within
"set_property -dict [ list CONFIG.CONST_VAL {6148914689804861440} CONFIG.CONST_WIDTH {32} ] $dma_irq_config"
(procedure "create_hier_cell_static_region" line 106)
invoked from within
"create_hier_cell_static_region [current_bd_instance .] static_region"
(procedure "create_root_design" line 62)
invoked from within
"create_root_design """
(file "/homes/mkaiser/Projekte/refdesign_xilinx_kcu1500_dynamic_5_0_2018.1/sources/bd/xilinx_kcu1500_dynamic_5_0_static.tcl" line 1993)

while executing
"source ${sourcesDir}/bd/xilinx_kcu1500_dynamic_5_0_static.tcl"
(file "create_design.tcl" line 130)

while executing
"source create_design.tcl"
(file "run.tcl" line 55)
update_compile_order -fileset sources_1
set_property location {179 439} [get_bd_ports PMBUS_ALERT]
undo
INFO: [Common 17-17] undo 'set_property location {179 439} [get_bd_ports PMBUS_ALERT]'
exit
INFO: [Common 17-206] Exiting Vivado at Fri Apr 27 10:44:27 2018...

 

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Visitor kencrocker
Visitor
911 Views
Registered: ‎12-08-2014

Re: Errors in SDAccel 2018.1 platform development reference design (UG1164)

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Hi,

 

This problem will be solved by modifying the .tcl file

 

/homes/mkaiser/Projekte/refdesign_xilinx_kcu1500_dynamic_5_0_2018.1/sources/bd/xilinx_kcu1500_dynamic_5_0_static.tcl

 as follows

 

Replace:

 

  # Create instance: dma_irq_config, and set properties
  set dma_irq_config [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant dma_irq_config ]
  set_property -dict [ list \
   CONFIG.CONST_VAL {6148914689804861440} \
   CONFIG.CONST_WIDTH {32} \
 ] $dma_irq_config

 

with

 

  # Create instance: dma_irq_config, and set properties
  set dma_irq_config [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant dma_irq_config ]
  set_property -dict [ list \
   CONFIG.CONST_VAL {4294967295} \
   CONFIG.CONST_WIDTH {32} \
 ] $dma_irq_config

 

The dsa block diagram should build succesfully using 2018.1 after this change.

 

Ken

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4 Replies
Moderator
Moderator
1,323 Views
Registered: ‎03-27-2012

Re: Errors in SDAccel 2018.1 platform development reference design (UG1164)

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Hi @mkaiser

 

As far as I know, the latest release version of SDx is 2017.4.
So the dsa ref-design should be based on 2017.4, not 2018.1.

 

Regards,

Sean

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Participant mkaiser
Participant
1,314 Views
Registered: ‎07-24-2017

Re: Errors in SDAccel 2018.1 platform development reference design (UG1164)

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hi seanz, 

 

thank you for your answer. It seems like the package has been revoked. I downloaded Xilinx_SDx_2018.1_0405_1.tar.gz two weeks ago...

 

Could you check in on that?

 

 

edit: checked my installation: see screenshot and xocc version. Now I am kind of confused...

 

$ xocc -v

** xocc v2018.1 (64-bit)
  ** SW Build 2188600 on Wed Apr  4 18:39:19 MDT 2018
     Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
sdx2018.1.png
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Moderator
Moderator
1,290 Views
Registered: ‎03-27-2012

Re: Errors in SDAccel 2018.1 platform development reference design (UG1164)

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Hi,

 

The package you installed is for SDSoC only.
If you want to use SDAccel you need to roll back to 2017.4.

 

Regards,
Sean

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Don’t forget to reply, kudo, and accept as solution.
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0 Kudos
Visitor kencrocker
Visitor
912 Views
Registered: ‎12-08-2014

Re: Errors in SDAccel 2018.1 platform development reference design (UG1164)

Jump to solution

Hi,

 

This problem will be solved by modifying the .tcl file

 

/homes/mkaiser/Projekte/refdesign_xilinx_kcu1500_dynamic_5_0_2018.1/sources/bd/xilinx_kcu1500_dynamic_5_0_static.tcl

 as follows

 

Replace:

 

  # Create instance: dma_irq_config, and set properties
  set dma_irq_config [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant dma_irq_config ]
  set_property -dict [ list \
   CONFIG.CONST_VAL {6148914689804861440} \
   CONFIG.CONST_WIDTH {32} \
 ] $dma_irq_config

 

with

 

  # Create instance: dma_irq_config, and set properties
  set dma_irq_config [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant dma_irq_config ]
  set_property -dict [ list \
   CONFIG.CONST_VAL {4294967295} \
   CONFIG.CONST_WIDTH {32} \
 ] $dma_irq_config

 

The dsa block diagram should build succesfully using 2018.1 after this change.

 

Ken

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