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Explorer
Explorer
1,235 Views
Registered: ‎06-17-2012

How to ensure burst write when part of the data needs to be written?

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I have a 512bit gmem port, and I need to update only part of the 512bit data each time.

In order to avoid writing back wrong result back to the memory, I read the 512bit data first and then 

modify part of the data. Finally I have the whole data written back to memory. 

However, I found that the tools fail to infer burst as the II > 1 caused by the data dependency between the read and write. 

Any suggestions on this problem?

Really appreciated.

 

Here is the code segment.

 

#define VLEN 16
#define LOG2_VLEN 4

typedef unsigned int uint;
typedef struct uint32_struct{
    unsigned int data[16];
} bus32_dt;


static void write_mem(
        bus32_dt *output,
        const int burst_num,
        const int burst_len,
        const int base_addr,
        const int inc,
        const int stride
        )
{
    for(int i = 0; i < burst_num; i++){
        uint addr_start = base_addr + i * stride;
        uint addr_end = addr_start + burst_len;
        uint burst_start = addr_start >> LOG2_VLEN;
        uint burst_end = (addr_end >> LOG2_VLEN) + 1;
        uint burst_len = burst_end - burst_start;
        for(int j = 0; j < burst_len; j++){
#pragma HLS LOOP_FLATTEN off
#pragma HLS pipeline II=1
            bus32_dt word = output[burst_start + j];
#pragma HLS ARRAY_PARTITION variable=word complete dim=1
            uint base = (burst_start + j) << LOG2_VLEN;
            for(int k = 0; k < VLEN; k++){
                int addr = base + k;
                if(addr >= addr_start && addr < addr_end){
                    word.data[k] = inc;
                }
            }
            output[burst_start+j] = word;
        }
    }
 }

 

Regards,

Cheng Liu

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1 Solution

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Moderator
Moderator
1,796 Views
Registered: ‎03-27-2012

Re: How to ensure burst write when part of the data needs to be written?

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Hi Cheng,

 

It's impossible to achieve random access of DDR in single clock on a single gmem.

That's why the II > 1.

Can you split the output to two one-way ports and assign them to different gmems?

 

Regards,

Sean

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4 Replies
Explorer
Explorer
1,219 Views
Registered: ‎04-12-2017

Re: How to ensure burst write when part of the data needs to be written?

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Hi,

 

Isn't it possible for you to use byte enable signals for this port?

Avi Chami MSc
FPGA Site
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Explorer
Explorer
1,190 Views
Registered: ‎06-17-2012

Re: How to ensure burst write when part of the data needs to be written?

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Yes, byte enable will be the ideal solution.

The problem is there is no clear byte enable support from the HLS tool chain. 

 

Regards,

Cheng Liu

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Moderator
Moderator
1,797 Views
Registered: ‎03-27-2012

Re: How to ensure burst write when part of the data needs to be written?

Jump to solution

Hi Cheng,

 

It's impossible to achieve random access of DDR in single clock on a single gmem.

That's why the II > 1.

Can you split the output to two one-way ports and assign them to different gmems?

 

Regards,

Sean

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Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

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Explorer
Explorer
1,146 Views
Registered: ‎06-17-2012

Re: How to ensure burst write when part of the data needs to be written?

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Hi, Sean,

 

Thanks for the suggestion.

Yes, having dual gmem in a single function or splitting them to dependent data flow functions improves the bandwidth utilization significantly.

 

Regards,

Cheng Liu

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