UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor pangudovskiy
Visitor
2,718 Views
Registered: ‎01-26-2017

How to increase the span of Pblock 'pblock_u_ocl_region' ?

Jump to solution

Hi, I am running openCL compilation for xilinx_adm-pcie-ku3_2ddr_3_2 board with pretty high BRAM utilization. Though I know I have enough BRAMs for kernel (pblock_u_ocl_region) and ddr mem (pblock_ddrmem/pblock_ddrmem2), xocc/Vivado fails to place design because somewhere pblock constraints are generated with pblock_u_ocl_region limited only by 648 BRAMs out of total 1080. Is there any way to change default "pblock_u_ocl_region" constraint? Cannot find where it comes from... Should be somewhere in board firmware?

 

xocc log:

ERROR: [XOCC 17-69] Command failed: Run 'impl_1' failed. Unable to open

ERROR: [XOCC 30-640] Place Check : This design requires more RAMB36/FIFO cells than are available in Pblock 'pblock_u_ocl_region'. This design requires 724 of such cell types but only 648 compatible sites are available in Pblock 'pblock_u_ocl_region'. Please consider increasing the span of Pblock 'pblock_u_ocl_region' or removing cells from it.
ERROR: [XOCC 30-640] Place Check : This design requires more RAMB18 and RAMB36/FIFO cells than are available in Pblock 'pblock_u_ocl_region'. This design requires 1454 of such cell types but only 1296 compatible sites are available in Pblock 'pblock_u_ocl_region'. Please consider increasing the span of Pblock 'pblock_u_ocl_region' or removing cells from it.
ERROR: [XOCC 30-640] Place Check : This design requires more RAMB36E2 cells than are available in Pblock 'pblock_u_ocl_region'. This design requires 724 of such cell types but only 648 compatible sites are available in Pblock 'pblock_u_ocl_region'. Please consider increasing the span of Pblock 'pblock_u_ocl_region' or removing cells from it.
ERROR: [XOCC 30-99] Placer failed with error: 'Implementation Feasibility check failed, Please see the previously displayed individual error or warning messages for more details.'

0 Kudos
1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
4,754 Views
Registered: ‎08-17-2011

Re: How to increase the span of Pblock 'pblock_u_ocl_region' ?

Jump to solution

Hi @pangudovskiy

 

Try changing DSA to xilinx:adm-pcie-ku3:2ddr-xpr:3.2 and see if it helps; otherwise as already mentioned you need to reduce kernel BRAM usage; maybe reduce by a factor of 2... your current needs of ~700 of RAMB36 (each 4 K bytes) means you need ~2.8 M Bytes this is huge.. maybe you design won't place and route in the FPGA, even if you had the necessary BRAMs.
 

I hope this helps.

 

- Hervé

SIGNATURE:
* New Dedicated Vivado HLS forums* http://forums.xilinx.com/t5/High-Level-Synthesis-HLS/bd-p/hls
* Readme/Guidance* http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

* Please mark the Answer as "Accept as solution" if information provided is helpful.
* Give Kudos to a post which you think is helpful and reply oriented.

View solution in original post

0 Kudos
3 Replies
Xilinx Employee
Xilinx Employee
2,692 Views
Registered: ‎08-01-2008

Re: How to increase the span of Pblock 'pblock_u_ocl_region' ?

Jump to solution
This seems resource limitation issue. Your require to increase memory size by using higher device or reduce usage of memory in your design..

In your target device only 648 compatible sites but you require 724 so its fitment issue.
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
0 Kudos
Xilinx Employee
Xilinx Employee
4,755 Views
Registered: ‎08-17-2011

Re: How to increase the span of Pblock 'pblock_u_ocl_region' ?

Jump to solution

Hi @pangudovskiy

 

Try changing DSA to xilinx:adm-pcie-ku3:2ddr-xpr:3.2 and see if it helps; otherwise as already mentioned you need to reduce kernel BRAM usage; maybe reduce by a factor of 2... your current needs of ~700 of RAMB36 (each 4 K bytes) means you need ~2.8 M Bytes this is huge.. maybe you design won't place and route in the FPGA, even if you had the necessary BRAMs.
 

I hope this helps.

 

- Hervé

SIGNATURE:
* New Dedicated Vivado HLS forums* http://forums.xilinx.com/t5/High-Level-Synthesis-HLS/bd-p/hls
* Readme/Guidance* http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

* Please mark the Answer as "Accept as solution" if information provided is helpful.
* Give Kudos to a post which you think is helpful and reply oriented.

View solution in original post

0 Kudos
Visitor pangudovskiy
Visitor
2,655 Views
Registered: ‎01-26-2017

Re: How to increase the span of Pblock 'pblock_u_ocl_region' ?

Jump to solution
herver, thanks a lot! OCL region in xilinx:adm-pcie-ku3:2ddr-xpr:3.2 covers almost all area and 40% of BRAM is not wasted like in xilinx:adm-pcie-ku3:2ddr:3.2.
0 Kudos