UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer radhikamkr
Observer
2,018 Views
Registered: ‎07-19-2018

Integration error while building project in SDSoC

Jump to solution

Hi,

When I was building a project in SDSoC, I am getting the following errors:


make: *** [all] Error 1    frontend_system             C/C++ Problem
make: *** [frontend.elf] Error 1    frontend             C/C++ Problem
recipe for target 'frontend.elf' failed    makefile    /frontend/Release    line 45    C/C++ Problem
SdsCompiler 83-5004: Build failed    frontend             C/C++ Problem
SdsCompiler 83-5019:compiler.deleteDefaultReportConfigs=false" '    frontend        line 0    C/C++ Problem
VPL 60-704: Integration error, problem implementing dynamic region, route_design ERROR    frontend             C/C++ Problem
VPL 60-806: Failed to finish platform linker    frontend             C/C++ Problem
VPL-4: Design failed to meet timing.    frontend             C/C++ Problem

 

Can anyone please suggest how to resolve these errors?

Thanks.

 

 

 

0 Kudos
1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
1,105 Views
Registered: ‎08-20-2018

Re: Integration error while building project in SDSoC

Jump to solution

Hi @microlijun 

I checked your report, in your design slack is slightly more.

Please try below option and let me know if it helps.

sds++ -xp "vivado_prop:run.impl_1.{STEPS.PLACE_DESIGN.ARGS.MORE OPTIONS}={-fanout_opt}"

fanout_opt_xp_param.PNG

 

Best Regards,
Nutan
-------------------------------------------------------------------------------
Please don't forget to reply, kudo and accept as a solution
17 Replies
Teacher xilinxacct
Teacher
1,976 Views
Registered: ‎10-23-2018

Re: Integration error while building project in SDSoC

Jump to solution

@radhikamkr

Most of these look like they stem from the same root cause... look in frontend and resolve that error, and things will look much better.

0 Kudos
Observer radhikamkr
Observer
1,971 Views
Registered: ‎07-19-2018

Re: Integration error while building project in SDSoC

Jump to solution

Can you suggest any possible errors?

The code is running fine in Vivado_HLS. But giving these errors in SDSoC.

 

Thanks.

Tags (1)
0 Kudos
Xilinx Employee
Xilinx Employee
1,912 Views
Registered: ‎08-20-2018

Re: Integration error while building project in SDSoC

Jump to solution

Hi @radhikamkr

 

Looks like the design has got timing violations.

Please add explore directive and give it a try.

sds++ -xp "vivado_prop:run.impl_1.{STEPS.PHYS_OPT_DESIGN.ARGS.MORE OPTIONS}={-directive Explore}" -xp "vivado_prop:run.impl_1.{STEPS.ROUTE_DESIGN.ARGS.MORE OPTIONS}={-directive Explore}"

Refer below screenshot

xp_params_explore_directive.PNG

Best Regards,
Nutan
-------------------------------------------------------------------------------
Please don't forget to reply, kudo and accept as a solution
0 Kudos
Observer radhikamkr
Observer
1,902 Views
Registered: ‎07-19-2018

Re: Integration error while building project in SDSoC

Jump to solution

Sorry,But what does this directive do?

Thanks.

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
1,888 Views
Registered: ‎08-20-2018

Re: Integration error while building project in SDSoC

Jump to solution

Hi @radhikamkr

When there are timing violations in your design, it means that timing requirements were not met for all paths in your design.

If the Vivado router is run with the EXPLORE directive, it can add additional clock roots to a net in order to improve the quality of the results.

 

Best Regards,
Nutan
-------------------------------------------------------------------------------
Please don't forget to reply, kudo and accept as a solution
Observer radhikamkr
Observer
1,886 Views
Registered: ‎07-19-2018

Re: Integration error while building project in SDSoC

Jump to solution

I tried adding the directive. But of no use.

The functions when hardware accelerated individually, are working fine. The trouble comes when all the functions are called inside a function and the top function is hardware accelerated.

I am attaching my code below.

Can you please look into it if possible.

Thanks.

0 Kudos
Xilinx Employee
Xilinx Employee
1,870 Views
Registered: ‎08-20-2018

Re: Integration error while building project in SDSoC

Jump to solution

Hi @radhikamkr

Please send the timing report  *_timing_summary.rpt

 

Best Regards,
Nutan
-------------------------------------------------------------------------------
Please don't forget to reply, kudo and accept as a solution
0 Kudos
Observer radhikamkr
Observer
1,856 Views
Registered: ‎07-19-2018

Re: Integration error while building project in SDSoC

Jump to solution

When I inline the functions the timing error is coming. When I remove it there is no timing error. But resource utilization is going up. Why is this happening?

Sorry, I couldn't locate the timing report.

Thanks.

0 Kudos
Xilinx Employee
Xilinx Employee
1,842 Views
Registered: ‎08-20-2018

Re: Integration error while building project in SDSoC

Jump to solution

Hi @radhikamkr

In your project folder based on your build configuration, there will be a Debug or Release Folder, inside it, there should be _sds folder. You can find timing report inside that

Best Regards,
Nutan
-------------------------------------------------------------------------------
Please don't forget to reply, kudo and accept as a solution
0 Kudos
Xilinx Employee
Xilinx Employee
1,659 Views
Registered: ‎08-20-2018

Re: Integration error while building project in SDSoC

Jump to solution

Hi @radhikamkr

Is the issue resolved?

I can help you to solve the issue if you provide the timing report.

Best Regards,
Nutan
-------------------------------------------------------------------------------
Please don't forget to reply, kudo and accept as a solution
0 Kudos
Observer radhikamkr
Observer
1,342 Views
Registered: ‎07-19-2018

Re: Integration error while building project in SDSoC

Jump to solution

Yes the issue was resolved.

I was calling all the functions inside a top function with inline pragma applied to all the functions.

It was causing the timing error.

 

0 Kudos
Visitor microlijun
Visitor
1,189 Views
Registered: ‎11-29-2018

Re: Integration error while building project in SDSoC

Jump to solution

@nutang 

Hi, I was migrating my OpenCV application to xfOpenCV. My design also have timming issue. I got the following error when build with SDx2018.2. How can I fix this? By the way, I did not find any timing_summary.rpt

***********************************************

......


[20:43:27] Starting logic routing..
[20:43:52] Phase 1 Build RT Design
[20:44:59] Phase 2 Router Initialization
[20:44:59] Phase 2.1 Fix Topology Constraints
[20:44:59] Phase 2.2 Pre Route Cleanup
[20:45:05] Phase 2.3 Global Clock Net Routing
[20:45:17] Phase 2.4 Update Timing
[20:46:49] Phase 2.5 Update Timing for Bus Skew
[20:46:49] Phase 2.5.1 Update Timing
[20:47:13] Phase 3 Initial Routing
[20:48:03] Phase 4 Rip-up And Reroute
[20:48:03] Phase 4.1 Global Iteration 0
[20:53:20] Phase 4.2 Global Iteration 1
[20:55:27] Phase 4.3 Global Iteration 2
[20:56:10] Phase 5 Delay and Skew Optimization
[20:56:10] Phase 5.1 Delay CleanUp
[20:56:10] Phase 5.1.1 Update Timing
[20:56:41] Phase 5.2 Clock Skew Optimization
[20:56:47] Phase 6 Post Hold Fix
[20:56:47] Phase 6.1 Hold Fix Iter
[20:56:47] Phase 6.1.1 Update Timing
[20:57:17] Phase 7 Route finalize
[20:57:17] Phase 8 Verifying routed nets
[20:57:17] Phase 9 Depositing Routes
[20:57:41] Phase 10 Leaf Clock Prog Delay Opt
[20:58:48] Phase 10.1 Delay CleanUp
[20:58:48] Phase 10.1.1 Update Timing
[20:59:49] Phase 10.2 Hold Fix Iter
[20:59:55] Phase 10.2.1 Update Timing
[21:01:21] Phase 11 Depositing Routes
[21:01:39] Phase 12 Post Router Timing
[21:02:22] Phase 13 Physical Synthesis in Router
[21:02:22] Phase 13.1 Physical Synthesis Initialization
[21:03:48] Phase 13.2 Critical Path Optimization
[21:03:54] Phase 14 Route finalize
[21:03:54] Finished 5th of 6 tasks (FPGA routing). Elapsed time: 00h 20m 26s

[16:40:23] Starting bitstream generation..

===>The following messages were generated while Compiling (bitstream) accelerator binary: bin Log file: /home/jun/workspace_sdx/VideoFusion/Release/_sds/p0/vivado/prj/prj.runs/impl_1/runme.log :
ERROR: [VPL-4] Design failed to meet timing.
Failed timing checks (paths):
{zcu102_rv_ss_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK --> zcu102_rv_ss_i/axi_interconnect_hpm0/m14_couplers/auto_cc/inst/gen_clock_conv.gen_sync_conv.gen_conv_write_ch.w_sync_clock_converter/gen_sync_clock_converter.m_tvalid_r_reg/D}

Please check the routed checkpoint (dr_routed_timing.dcp) and timing summary report (dr_timing_summary.rpt) for more information.
ERROR: [VPL 60-704] Integration error, problem implementing dynamic region, route_design ERROR
ERROR: [VPL 60-806] Failed to finish platform linker
ERROR: [SdsCompiler 83-5019] Exiting sds++ : Error when calling '/home/jun/Programs/Xilinx2018.2/SDx/2018.2/bin/vpl --iprepo /home/jun/workspace_sdx/VideoFusion/Release/_sds/iprepo/repo --iprepo /home/jun/Programs/Xilinx2018.2/SDx/2018.2/data/ip/xilinx --platform /home/jun/zcu102-rv-ss-2018-2/zcu102_rv_ss/zcu102_rv_ss.xpfm --temp_dir /home/jun/workspace_sdx/VideoFusion/Release/_sds/p0 --output_dir /home/jun/workspace_sdx/VideoFusion/Release/_sds/p0/vpl --input_file /home/jun/workspace_sdx/VideoFusion/Release/_sds/p0/.xsd/top.bd.tcl --target hw --save_temps --kernels w0_xf_boxFilter:w3_xf_add:w2_xf_subtract:w1_xf_multiply:w4_xf_calcHist:adapter --webtalk_flag SDSoC --remote_ip_cache /home/jun/workspace_sdx/ip_cache --xp "vivado_prop:run.impl_1.{STEPS.PHYS_OPT_DESIGN.ARGS.MORE OPTIONS}={-directive Explore}" --xp "vivado_prop:run.impl_1.{STEPS.ROUTE_DESIGN.ARGS.MORE OPTIONS}={-directive Explore}" --xp "param:compiler.deleteDefaultReportConfigs=false" '
sds++ log file saved as /home/jun/workspace_sdx/VideoFusion/Release/_sds/reports/sds.log
ERROR: [SdsCompiler 83-5004] Build failed
sds++ completed at Tue Mar 19 16:45:02 UTC 2019

0 Kudos
Xilinx Employee
Xilinx Employee
1,149 Views
Registered: ‎08-20-2018

Re: Integration error while building project in SDSoC

Jump to solution

Hi @microlijun 

Go to Debug or Release folder based on your active build configuration.

Navigate to _sds/p0/vivado/prj/prj.runs/impl_1

Please check for dr_timing_summary.rpt

Send it to me.

Best Regards,
Nutan
-------------------------------------------------------------------------------
Please don't forget to reply, kudo and accept as a solution
0 Kudos
Visitor microlijun
Visitor
1,133 Views
Registered: ‎11-29-2018

Re: Integration error while building project in SDSoC

Jump to solution

Hi @nutang 

Here is the timing report. Thank you.

 

Best Regards,

Jun

0 Kudos
Xilinx Employee
Xilinx Employee
1,106 Views
Registered: ‎08-20-2018

Re: Integration error while building project in SDSoC

Jump to solution

Hi @microlijun 

I checked your report, in your design slack is slightly more.

Please try below option and let me know if it helps.

sds++ -xp "vivado_prop:run.impl_1.{STEPS.PLACE_DESIGN.ARGS.MORE OPTIONS}={-fanout_opt}"

fanout_opt_xp_param.PNG

 

Best Regards,
Nutan
-------------------------------------------------------------------------------
Please don't forget to reply, kudo and accept as a solution
Visitor microlijun
Visitor
1,029 Views
Registered: ‎11-29-2018

Re: Integration error while building project in SDSoC

Jump to solution

Hi @nutang ,

It works. Thank you so much.

0 Kudos
Xilinx Employee
Xilinx Employee
928 Views
Registered: ‎08-20-2018

Re: Integration error while building project in SDSoC

Jump to solution

Hi @microlijun 

Please accept my post as a solution.

https://forums.xilinx.com/t5/SDSoC-Environment-and-reVISION/Integration-error-while-building-project-in-SDSoC/m-p/954106/highlight/true#M3784

Best Regards,
Nutan
-------------------------------------------------------------------------------
Please don't forget to reply, kudo and accept as a solution
0 Kudos