Hi!
I am using KU1500 with SDAccel 2017.2.
It is known that SDAccel can automaticaly lower kernel frequency if your SDAccel design doesn't meet timings.
So why SDAccel can asks for change this clock by hands by setting --kernel-frquency switch, like in this SDAccel build logs?
Creating Vivado project and starting FPGA synthesis.
.........................................................................................................................................................................
Finished 1st of 5 tasks (FPGA synthesis). Elapsed time: 00h 41m 44s.
.....................
Finished 2nd of 5 tasks (FPGA logic optimization). Elapsed time: 00h 17m 59s.
...........................
Finished 3rd of 5 tasks (FPGA logic placement). Elapsed time: 00h 30m 53s.
.............................
Finished 4th of 5 tasks (FPGA routing). Elapsed time: 01h 24m 50s.
===>The following messages were generated while Compiling (bitstream) opencl binary: binary_container_1 Log file: /home/smith/workspace_2017.2/conv_cnn/System/_xocc_link_binary_container_1/impl/build/system/binary_container_1/bitstream/binary_container_1_ipi/ipiimpl/ipiimpl.runs/impl_1/runme.log :
ERROR: [XOCC-1] design did not meet timing, auto frequency scaling failed because an unscalable system clock did not meet the target frequency. Please try specifying a clock frequency lower than 300 using the '--kernel_frequency' switch for the next compilation
ERROR: [XOCC 60-704] Integration error, problem implementing dynamic region, route_design ERROR
ERROR: [XOCC 60-626] Kernel link failed to complete
ERROR: [XOCC 60-703] Failed to finish linking
make: *** [binary_container_1.xclbin] Ошибка 1
And what is the"unscalable" frequency of which SDAccel are talking about?
