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Observer keener_cc
Observer
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Registered: ‎02-10-2017

SDAccel platform development UG1164 incomplete instructions

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I am attempting to create the board files and FPGA target image logic for a custom board to become an SDAccel target.  There are several settings or components referenced in UG1164 (latest v2018.1) that are not available when creating the logic design for an XCKU15P device. 

 

In particular, the PF_DEMUX (or dma_pf_demux) IP and the multiple physical functions setting for the XDMA IP core are not available.

 

Is there an IP setting that can be set, or some other "hidden" setting to enable the functions that are described in UG1164? Are these IP blocks and settings only available for some devices (XCVU*P, etc.)?

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Moderator
Moderator
872 Views
Registered: ‎11-04-2010

Re: SDAccel platform development UG1164 incomplete instructions

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Now UG1164 is off-line and any question for UG1164 is not supported on the forum.

If you need UG1164 or support for UG1164, please contact sales account team.

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Moderator
Moderator
873 Views
Registered: ‎11-04-2010

Re: SDAccel platform development UG1164 incomplete instructions

Jump to solution

Now UG1164 is off-line and any question for UG1164 is not supported on the forum.

If you need UG1164 or support for UG1164, please contact sales account team.

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

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