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Observer kemache
Observer
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Registered: ‎05-07-2018

configure the PL clock in SDSOC 2018.2

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Hello,

I am a new in SDSoC developpment environment.

To implement my design I am using the zedboard. When building, my design doesn't met timing (at 100MHz) so I want to lower the frequency in SDSoC environment. Is it possible or I have necessary to create a new platform in Vivado with the frequency I desire then use it in SDSoC?

Thanks for your responses.

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Xilinx Employee
Xilinx Employee
620 Views
Registered: ‎08-20-2018

Re: configure the PL clock in SDSOC 2018.2

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Hi @kemache

Slack is not less -> it is -0.278 (violation), So we need to fix this.

You cannot use skip timing xp parameter.

However you can try various options which I mentioned before (different directives)

If that doesn't help you might need to create the new platform  as you mentioned before.

 

 

 

Best Regards,
Nutan
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Xilinx Employee
Xilinx Employee
680 Views
Registered: ‎08-20-2018

Re: configure the PL clock in SDSOC 2018.2

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Hi @kemache

I consider you have declared various clock IDs while creating a platform.

When you navigate to project.sdx, you can see below window,

clock change.PNG

However, before that I would like to tell you an option to optimize the timing.

Please navigate to C/C++ Build Settings->C/C++ Build-> Settings->SDS++ linker 

add xp parameter in GUI as mentioned below.

sds++ -xp "vivado_prop:run.impl_1.{STEPS.PHYS_OPT_DESIGN.ARGS.MORE OPTIONS}={-directive Explore}" -xp "vivado_prop:run.impl_1.{STEPS.ROUTE_DESIGN.ARGS.MORE OPTIONS}={-directive Explore}"

xp_params_explore_directive.PNG

If the slack is less, you can also add option to skip timing analysis,

-xp param:compiler.skipTimingCheckAndFrequencyScaling=1

skip_time_param.png

Best Regards,
Nutan
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Observer kemache
Observer
669 Views
Registered: ‎05-07-2018

Re: configure the PL clock in SDSOC 2018.2

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Hi @nutang

Thanks a lot for your response, it is very helpful.

Please I need your confirmation in what I have understood. 

If I have an SDSoC application containing a hardware accelerator and I dont want to skip the timing analysis and I have choose a predefined hadware platform: zed with 4 clock IDs (100MHz, 142 MHz, 166MHz and 200MHz). For the hardware accelerator I use the clock ID of 100MHz. When building the application the timing is not met. 

So if I want the hardware accelerator to work at the frequency of 70MHz I have inevitably to create a new platform in Vivado with a clock ID of 70MHz and then include it to SDSoC ?

Best regards,

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Xilinx Employee
Xilinx Employee
660 Views
Registered: ‎08-20-2018

Re: configure the PL clock in SDSOC 2018.2

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Hi @kemache

If you do not want to skip the timing, I would suggest you to analyze the timing report first. Based on analysis you can try first option mentioned in my previous post, it will optimize the timing. 

sds++ -xp "vivado_prop:run.impl_1.{STEPS.PHYS_OPT_DESIGN.ARGS.MORE OPTIONS}={-directive Explore}" -xp "vivado_prop:run.impl_1.{STEPS.ROUTE_DESIGN.ARGS.MORE OPTIONS}={-directive Explore}"

If explore directive doesn't help, you can analyse the timing report (techniques are documented below) and change the options and test.

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug906-vivado-design-analysis.pdf

eg. 

sds++ -xp "vivado_prop:run.impl_1.{STEPS.PHYS_OPT_DESIGN.ARGS.MORE OPTIONS}={-directive PerfOptimized_high}" -xp "vivado_prop:run.impl_1.{STEPS.ROUTE_DESIGN.ARGS.MORE OPTIONS}={-directive AreaOptimized_high}"

or

sds++ -xp "vivado_prop:run.impl_1.{STEPS.PHYS_OPT_DESIGN.ARGS.MORE OPTIONS}={-directive AreaOptimized_high}" -xp "vivado_prop:run.impl_1.{STEPS.ROUTE_DESIGN.ARGS.MORE OPTIONS}={-directive PerfOptimized_high}"

 

flow_options.png

If suppose fanout is more, you can optimize fanout

vivado_prop:run.impl_1.{STEPS.PLACE_DESIGN.ARGS.MORE OPTIONS}={-fanout_opt}

You can post the timing report here if possible, I can help you.

 

Best Regards,
Nutan
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Observer kemache
Observer
653 Views
Registered: ‎05-07-2018

Re: configure the PL clock in SDSOC 2018.2

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Hello @nutang

I tried the command in your first reply the slack is less but I still have the timing not met problem. 

Thank you for your help.

The timming summary is attached in this message.

Best regards,

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Xilinx Employee
Xilinx Employee
621 Views
Registered: ‎08-20-2018

Re: configure the PL clock in SDSOC 2018.2

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Hi @kemache

Slack is not less -> it is -0.278 (violation), So we need to fix this.

You cannot use skip timing xp parameter.

However you can try various options which I mentioned before (different directives)

If that doesn't help you might need to create the new platform  as you mentioned before.

 

 

 

Best Regards,
Nutan
-------------------------------------------------------------------------------
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Observer kemache
Observer
614 Views
Registered: ‎05-07-2018

Re: configure the PL clock in SDSOC 2018.2

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Hello @nutang

Thanks a lot for your help.

I mean that the slack this time is less than without using the directive of timing optimization (it was -0.561).

I will try the other directives you mentioned.

Best regards,

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Xilinx Employee
Xilinx Employee
609 Views
Registered: ‎08-20-2018

Re: configure the PL clock in SDSOC 2018.2

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Hi @kemache

Oh okay, got it.

Please let me know if any further help needed

Best Regards,
Nutan
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Observer kemache
Observer
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Registered: ‎05-07-2018

Re: configure the PL clock in SDSOC 2018.2

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Hi @nutang

I will, thanks a lot.

Best Regards,

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