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Visitor channinglan
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1,356 Views
Registered: ‎08-21-2017

github example : SDAccel_Examples/acceleration/kmeans issue

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sw_emu  is ok, but hw not ok



XILINX_SDX=/opt/Xilinx/SDx/2017.1
XILINX_OPENCL=/opt/Xilinx/SDx/2017.1
XILINX_VIVADO=/opt/Xilinx/SDx/2017.1/Vivado
LD_LIBRARY_PATH=/opt/Xilinx/SDx/2017.1/runtime/lib/x86_64:/opt/Xilinx/SDx/2017.1/lib/lnx64.o:/opt/Xilinx/SDx/2017.1/Vivado/lib/lnx64.o:/opt/Xilinx/SDx/2017.1/Vivado_HLS/lnx64/tools/opencv:/usr/lib/x86_64-linux-gnu:/opt/Xilinx/SDx/2017.1/runtime/lib/x86_64:/opt/Xilinx/SDx/2017.1/lib/lnx64.o:/opt/Xilinx/SDx/2017.1/Vivado/lib/lnx64.o:/opt/Xilinx/SDx/2017.1/Vivado_HLS/lnx64/tools/opencv:/usr/lib/x86_64-linux-gnu:/opt/Xilinx/SDx/2017.1/runtime/lib/x86_64:/opt/Xilinx/SDx/2017.1/lib/lnx64.o:/opt/Xilinx/SDx/2017.1/Vivado/lib/lnx64.o:/opt/Xilinx/SDx/2017.1/Vivado_HLS/lnx64/tools/opencv:/usr/lib/x86_64-linux-gnu:
PATH=/opt/Xilinx/SDx/2017.1/Vivado:/usr/lib/x86_64-linux-gnu:/opt/Xilinx/SDx/2017.1/bin/:/opt/Xilinx/SDx/2017.1/Vivado/data/sdx:/opt/Xilinx/SDx/2017.1/Vivado/bin:/opt/Xilinx/SDx/2017.1/Vivado:/usr/lib/x86_64-linux-gnu:/opt/Xilinx/SDx/2017.1/bin/:/opt/Xilinx/SDx/2017.1/Vivado/data/sdx:/opt/Xilinx/SDx/2017.1/Vivado/bin:/opt/Xilinx/SDx/2017.1/Vivado:/usr/lib/x86_64-linux-gnu:/opt/Xilinx/SDx/2017.1/bin/:/opt/Xilinx/SDx/2017.1/Vivado/data/sdx:/opt/Xilinx/SDx/2017.1/Vivado/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games
SDX_CXX_PATH=/usr/bin/g++
DSA=xilinx:kcu1500:4ddr-xpr:4.0
PLATFORM_PATH=/opt/Xilinx/SDx/2017.1/platforms
DSA_PLATFORM=xilinx_kcu1500_4ddr-xpr_4_0
HALLIB=libxclngdrv.so
LM_LICENSE_FILE=/home/iei/share/Xilinx/Xilinx_2c4d54cf0c49_170816.lic



 ---------------------------------------------------------------------
 do kmeans sample hw
 ---------------------------------------------------------------------
/home/iei/share/Xilinx/svn/Xilinx/git_example/SDAccel_Examples/acceleration/kmeans
-----------------------------------
make all TARGETS=hw DEVICES=xilinx:kcu1500:4ddr-xpr:4.0
-----------------------------------
mkdir -p xclbin
/opt/Xilinx/SDx/2017.1/bin/xocc -l --xp "param:compiler.preserveHlsOutput=1" --xp "param:compiler.generateExtraRunData=true" -s --nk kmeans:2  -o xclbin/kmeans.hw.xilinx_kcu1500_4ddr-xpr_4_0.xclbin -t hw --platform xilinx:kcu1500:4ddr-xpr:4.0 xclbin/kmeans.hw.xilinx_kcu1500_4ddr-xpr_4_0.xo

****** xocc v2017.1_sdx (64-bit)
  **** SW Build 1915620 on Thu Jun 22 17:54:59 MDT 2017
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

Attempting to get a license: ap_opencl
Feature available: ap_opencl
INFO: [XOCC 60-629] Linking for hardware target
INFO: [XOCC 60-895]    Target platform: /opt/Xilinx/SDx/2017.1/platforms/xilinx_kcu1500_4ddr-xpr_4_0/xilinx_kcu1500_4ddr-xpr_4_0.xpfm
INFO: [XOCC 60-423]   Target device: xilinx:kcu1500:4ddr-xpr:4.0
INFO: [XOCC 60-251]   Hardware accelerator integration...
Creating Vivado project and starting FPGA synthesis.
.....................................................................................................................................................................................................................................................
Finished 1st of 5 tasks (FPGA synthesis). Elapsed time: 00h 32m 12s.
.....................
Finished 2nd of 5 tasks (FPGA logic optimization). Elapsed time: 00h 12m 57s.
...........................
Finished 3rd of 5 tasks (FPGA logic placement). Elapsed time: 00h 32m 44s.
............................
Finished 4th of 5 tasks (FPGA routing). Elapsed time: 01h 12m 37s.


===>The following messages were generated while  Compiling (bitstream) opencl binary: kmeans.hw.xilinx_kcu1500_4ddr-xpr_4_0 Log file: /home/iei/share/Xilinx/svn/Xilinx/git_example/SDAccel_Examples/acceleration/kmeans/_xocc_link_kmeans.hw.xilinx_kcu1500_4ddr-xpr_4_0_kmeans.hw.xilinx_kcu1500_4ddr-xpr_4_0.dir/impl/build/system/kmeans.hw.xilinx_kcu1500_4ddr-xpr_4_0/bitstream/kmeans.hw.xilinx_kcu1500_4ddr-xpr_4_0_ipi/ipiimpl/ipiimpl.runs/impl_1/runme.log  :
ERROR: [XOCC-1] design did not meet timing, auto frequency scaling failed because an unscalable system clock did not meet the target frequency. Please try specifying a lower clock frequency using '--kernel_frequency 300' for the next compilation
ERROR: [XOCC 60-704] Integration error, problem implementing OCL region, route_design ERROR
ERROR: [XOCC 60-626] Kernel link failed to complete
ERROR: [XOCC 60-703] Failed to finish linking
../..//utility/rules.mk:128: recipe for target 'xclbin/kmeans.hw.xilinx_kcu1500_4ddr-xpr_4_0.xclbin' failed
make: *** [xclbin/kmeans.hw.xilinx_kcu1500_4ddr-xpr_4_0.xclbin] Error 1
sel hw
-----------------------------------
XCL_EMULATION_MODE=hw
LD_LIBRARY_PATH=/opt/Xilinx/SDx/2017.1/runtime/lib/x86_64/:/opt/Xilinx/SDx/2017.1/runtime/lib/x86_64:/opt/Xilinx/SDx/2017.1/lib/lnx64.o:/opt/Xilinx/SDx/2017.1/Vivado/lib/lnx64.o:/opt/Xilinx/SDx/2017.1/Vivado_HLS/lnx64/tools/opencv:/usr/lib/x86_64-linux-gnu:/opt/Xilinx/SDx/2017.1/runtime/lib/x86_64:/opt/Xilinx/SDx/2017.1/lib/lnx64.o:/opt/Xilinx/SDx/2017.1/Vivado/lib/lnx64.o:/opt/Xilinx/SDx/2017.1/Vivado_HLS/lnx64/tools/opencv:/usr/lib/x86_64-linux-gnu:
emconfigutil --xdevice 'xilinx:kcu1500:4ddr-xpr:4.0' --nd 1
-----------------------------------

****** configutil v2017.1_sdx (64-bit)
  **** SW Build 1915620 on Thu Jun 22 17:54:59 MDT 2017
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

INFO: [ConfigUtil 60-895]    Target platform: /opt/Xilinx/SDx/2017.1/platforms/xilinx_kcu1500_4ddr-xpr_4_0/xilinx_kcu1500_4ddr-xpr_4_0.xpfm
emulation configuration file `emconfig.json` is created in ./ directory
-----------------------------------
./host_kmeans -i ./data/100 -c ./data/100.gold_c5 -m 5 -n 5 -g 2
-----------------------------------

I/O completed

fileName=./data/100

Number of objects: 100
Number of features: 34
Number of min cluster: 5
Number of max cluster: 5
threshold: 0.001000
INFO: Importing xclbin/kmeans.hw.xilinx_kcu1500_4ddr-xpr_4_0.xclbin
ERROR: xclbin/kmeans.hw.xilinx_kcu1500_4ddr-xpr_4_0.xclbin xclbin not available please build

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Xilinx Employee
Xilinx Employee
1,833 Views
Registered: ‎07-18-2014

Re: github example : SDAccel_Examples/acceleration/kmeans issue

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hi @channinglan,

 

This timing issue do not exist in 2017.2, It should build with following warning for 2017.2:

WARNING: [XOCC 60-732] Link warning: One or more timing paths failed timing targeting 300 MHz for kernel clock 'DATA_CLK'. The frequency is being automatically changed to 235.6 MHz to enable proper functionality

 

 

For 2017.1, you can lower the kernel clock manually by adding following two lines in Makefile:

kmeans_CLFLAGS += --kernel_frequency=200

kmeans_LDCLFLAGS+=--kernel_frequency=200

 

Just add them after below code (line number: 54)
kmeans_LDCLFLAGS
=--nk kmeans:$(COMPUTE_UNITS)

View solution in original post

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3 Replies
Xilinx Employee
Xilinx Employee
1,834 Views
Registered: ‎07-18-2014

Re: github example : SDAccel_Examples/acceleration/kmeans issue

Jump to solution

hi @channinglan,

 

This timing issue do not exist in 2017.2, It should build with following warning for 2017.2:

WARNING: [XOCC 60-732] Link warning: One or more timing paths failed timing targeting 300 MHz for kernel clock 'DATA_CLK'. The frequency is being automatically changed to 235.6 MHz to enable proper functionality

 

 

For 2017.1, you can lower the kernel clock manually by adding following two lines in Makefile:

kmeans_CLFLAGS += --kernel_frequency=200

kmeans_LDCLFLAGS+=--kernel_frequency=200

 

Just add them after below code (line number: 54)
kmeans_LDCLFLAGS
=--nk kmeans:$(COMPUTE_UNITS)

View solution in original post

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Visitor channinglan
Visitor
1,128 Views
Registered: ‎08-21-2017

Re: github example : SDAccel_Examples/acceleration/kmeans issue

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add

kmeans_CLFLAGS += --kernel_frequency=200

kmeans_LDCLFLAGS+=--kernel_frequency=200

is ok...

 

but how to avoid this problem?

The reason is too crowded FPGA caused it?

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Xilinx Employee
Xilinx Employee
1,112 Views
Registered: ‎07-18-2014

Re: github example : SDAccel_Examples/acceleration/kmeans issue

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Hi,
Can you please be more specific to these questions?
- but how to avoid this problem?
- The reason is too crowded FPGA caused it?

Are you expecting, how to run kernel at 300MHz, without getting these warning?
or you are expecting that without specifying these extra option, it should build and auto-scale down the freq?

-Heera
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