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Contributor
Contributor
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Registered: ‎01-08-2020

mapping kernel ports to global memory

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Hi,

Im working on ALVEO U250 card, where im working on Vadd example to understand the vitis flow. The ports of Vadd are getting mapped to DDR[0] interface by default , i want to change the port mapping and utilise all the global memories. 

[connectivity]
sp=krnl_vadd.m_axi_gmem0:DDR[0]
sp=krnl_vadd.m_axi_gmem1:DDR[1]
sp=krnl_vadd.m_axi_gmem2:DDR[2]

I used this connectivity.sp option which is mentioned in UG 1393 document but still it is using only one DDR.


Data transfer between kernel(s) and global memory(s)
krnl_vadd_1:m_axi_gmem0-DDR[0] RD = 16.000 KB WR = 0.000 KB
krnl_vadd_1:m_axi_gmem1-DDR[0] RD = 16.000 KB WR = 0.000 KB
krnl_vadd_1:m_axi_gmem2-DDR[0] RD = 0.000 KB WR = 16.000 KB

In document it is mentioned that

During v++ linking, use the connectivity.sp option in a config file to map the kernel port to the desired memory bank.
 
There is no config file with .cfg extention. i can only find config-common.ini file. please help me out.
 
Regards
Prashanth.

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-16-2008

Re: mapping kernel ports to global memory

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You don't touch the auto-generated .ini files. Instead, you can create a file (any extension, .ini, .cfg, .txt...) with the connectivity options and then specify --config <your created configuration file> in v++ linker options.

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Xilinx Employee
Xilinx Employee
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Registered: ‎06-04-2018

Re: mapping kernel ports to global memory

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Hi @mdpuma ,

you can use the host_global_bandwidth example as reference : 

https://github.com/Xilinx/Vitis_Accel_Examples/tree/e2ea58df09d123214fb0d814fe605a412d146625/host/host_global_bandwidth

Following is the ini file where two banks are used(DDR[0], DDR[1]) :

https://github.com/Xilinx/Vitis_Accel_Examples/blob/e2ea58df09d123214fb0d814fe605a412d146625/host/host_global_bandwidth/krnl_host_global.ini

Need to add the ini file to ldclflags in Makefile: 

https://github.com/Xilinx/Vitis_Accel_Examples/blob/e2ea58df09d123214fb0d814fe605a412d146625/host/host_global_bandwidth/Makefile#L75

Regards,
Vishnu
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Contributor
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Registered: ‎01-08-2020

Re: mapping kernel ports to global memory

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Hi @bchebrol 

Thanks a lot for your reply . The make file which is there in github kernel_vadd example is not matching with the make file generated by the vitis tool. 

https://github.com/Xilinx/Vitis_Accel_Examples/blob/e2ea58df09d123214fb0d814fe605a412d146625/rtl_kernels/rtl_vadd/Makefile 

I have attached the make file generated by the tool and also i attached the screenshot of the .ini file  . There are several .ini files im confused which .ini file i should use.  please kindly look into this issue. ini file.png

Thanks & Regards

Prashanth.

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Xilinx Employee
Xilinx Employee
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Registered: ‎06-04-2018

Re: mapping kernel ports to global memory

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Hi @mdpuma ,

you see different ini files for each of the flows(Software Emulation, Hardware Emulation and Hardware). That is the reason you see several .ini files. 

Regards,
Vishnu
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Contributor
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Registered: ‎01-08-2020

Re: mapping kernel ports to global memory

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Hi @bchebrol 

As you told , I understood that .ini file will be generated for software emulation, hardware emulation and target hardware .  Would you please let me know in which .ini file I should write  connectivity.sp to map the global memories. 

 

Thanks and Regards,

Prashanth.

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-16-2008

Re: mapping kernel ports to global memory

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You don't touch the auto-generated .ini files. Instead, you can create a file (any extension, .ini, .cfg, .txt...) with the connectivity options and then specify --config <your created configuration file> in v++ linker options.

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Contributor
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Registered: ‎01-08-2020

Re: mapping kernel ports to global memory

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@gracesThanks a lot man.It worked..

 

Regards,

Prashanth

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Contributor
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Registered: ‎01-08-2020

Re: mapping kernel ports to global memory

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Hi @graces 

please clarify my doubt, I have given config file and build the hardware emulation and run it , then all the three DDRs as i mentioned in config file is being access by krnl_vadd input arguments . Below attachment-1 is the system diagram generated by vitis analyzer. I used the same config file in target hardware and built it. Then in vitis analyzer is showing that only one DDR is being accessed by krnl_vadd inputs. Please check the attachment 2 below. Can you please tell me if any specific reason for that?13.png

                                                                fig : attachment-1

 

12.png

                                               fig : attachment 2


 Que(2):

If I want to transfer the data from host to specific address location of  DDRs , I need to access the address locations of DDRs from host code.  In vitis analyzer base addresses of DDRs are given , can i use them in host code to transfer the data to/from DDRs.

Regards,

Prashanth.

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