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Observer te7a
Observer
1,664 Views
Registered: ‎05-26-2017

multiple memory banks

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I'm trying to apply the same steps in the watermark example but instead of using different memory banks for input and output of 1 kernel, I'm trying to use it for the same output but of 2 instances of the same kernel built in the xclbin, I used the XOCC linker options to assign each instance to a different DDR bank, like so:

--sp Kernel_1.m_axi_gmem:bank0 --sp Kernel_2.m_axi_gmem:bank1


I can see that when I do xbsak query as follows:
Mem Topology:
     Tag       Type          Base Address  Size (KB)
 [0] bank0     MEM_DDR4      0x0           0x1000000
 [1] bank2     **UNUSED**    0x800000000   0x1000000
 [2] bank3     **UNUSED**    0xc00000000   0x1000000
 [3] bank1     MEM_DDR4      0x400000000   0x1000000

so I believe my kernel side changes are valid:

now from the host code, I exactly followed the instructions and the example on github to use the flag CL_MEM_EXT_PTR_XILINX and cl_mem_ext_ptr_t with flags set to XCL_MEM_DDR_BANK0 and 1 respectivily, however I always get the following runtime error:

Memory bank mask specified for argument is "000000000000000000000001" while memory bank mask in binary is "000000000000000000001000".

and whatever I do with the flags in the host code (used BANK2, BANK3....etc ) the mask value in the error message doesn't change, as if the runtime is taking whatever I'm feeding in the flags and always replacing it with "000000000000000000000001". 

 

is there something wrong I'm doing here? or it is not possible to do it among multiple instances of the same kernel?

any thoughts?

 

Regards,

Ahmed

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1 Solution

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Moderator
Moderator
1,342 Views
Registered: ‎02-11-2014

Re: multiple memory banks

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Hello @te7a,

 

I am just closing the loop on this thread. I filed an Enhancement Request to get support added into a future release of SDx. We currently cannot replicate a single kernel into two separate instances and then put them onto two memory banks. A workaround is to uniquify the kernel names so they have their own dedicated AXI interface connections so you can then use two memory banks.

 

Thanks,
Cory

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7 Replies
Xilinx Employee
Xilinx Employee
1,649 Views
Registered: ‎01-11-2011

Re: multiple memory banks

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Hi @te7a, just as a check, are you applying the --sp options in the xocc -l (linker) stage? If you are using the GUI, there are two areas for selecting "Edit XOCC options", one on the kernel itself, and another for the container, which applies to the linker stage.

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Observer te7a
Observer
1,635 Views
Registered: ‎05-26-2017

Re: multiple memory banks

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I did my first trial in the gui from the rght click on the kernel itself, (which is by the way the way the watermark example is doing it!) but this didn't work (the options were ignored!)

 

then when I did it in the SDx XOCC Kernel Linker miscellaneous settings it did seem to have the effect on the xclbin when I do the xbsak query!

 

I don't know how the watermark example on github got it working as a compiler option though!!

 

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Observer te7a
Observer
1,633 Views
Registered: ‎05-26-2017

Re: multiple memory banks

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Oh I see now!!!!

the XOCC option on the kernel is a compiler, on the container is a linker, it wasn't very obvious!

 

anyway, I added it as Other Flags in the miscellaneous SDx XOCC Kernel Linker settings, I think it has the same effect.

 

the issue I'm having is on the host side, where XCL_MEM_DDR_BANK0 and BANK1 are used

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Xilinx Employee
Xilinx Employee
1,596 Views
Registered: ‎07-16-2008

Re: multiple memory banks

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For OpenCL kernel, can you also try adding --max_memory_ports option to the kernel compile options?

--max_memory_ports <kernel_name>

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Observer te7a
Observer
1,565 Views
Registered: ‎05-26-2017

Re: multiple memory banks

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I know that the max memory port option is for opencl kernels only, I'm using a c++/hls kernel.

 

so far, it looks like the multi-memory bank support feature is broken. 

 

if you use it exactly like the watermarking example, it will work, but if you want to use it on same port names from different compute kernel instances, you will get a xclbin file that seems to have the interfaces to DDR banks right, but your host code will never be able to allocate the buffers for the compute kernels on the proper banks using the xilinx memory extensions flags

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Observer te7a
Observer
1,564 Views
Registered: ‎05-26-2017

Re: multiple memory banks

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any by the way, another bug in the GUI when I tried to revert the XOCL linker settings to use only 1 memory bank again:

https://forums.xilinx.com/t5/SDAccel/SDAccel-2018-2-GUI-problem/m-p/890456

 

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Moderator
Moderator
1,343 Views
Registered: ‎02-11-2014

Re: multiple memory banks

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Hello @te7a,

 

I am just closing the loop on this thread. I filed an Enhancement Request to get support added into a future release of SDx. We currently cannot replicate a single kernel into two separate instances and then put them onto two memory banks. A workaround is to uniquify the kernel names so they have their own dedicated AXI interface connections so you can then use two memory banks.

 

Thanks,
Cory

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