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Observer
Observer
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Registered: ‎05-31-2018

on-chip global BRAMs memory example from xilinx documents is failed in SDSoC 2018.2

 

Hi,

I am trying to use on-chip global memory in my kernel design, but first, I tried this example that is provided in  https://www.xilinx.com/support/documentation/sw_manuals/ug1207-sdaccel-performance-optimization.pdf (page 83), to run on ultrascale plus board zcu102.

However, that did not compiled and I got this error

 

ERROR: [KernelCheck 83-113] Kernel 'vadd_dataIn' accesses non-pipe global variable 'xcl_mem_g_var0', which is not supported.

Error: unable to create function map for HLS kernel vadd

 

Note: If I run the project using the emulator, it works fine !!!! however, trying to generate the bitstream gave the above error.

 

Does anyone have an idea on how to solve this error and get the example works? And what does it mean

 

I have attached the host and the opencl kernel source code.

 

I am using SDSoC 2018.2

and my system is ubuntu 16.04


-------------------------------------------------------------------

My kernel code is :

#define N 10

global int g_var0[10];
global int g_var1[10];
global int g_var2[10];

__kernel void __attribute__((reqd_work_group_size(1,1,1)))
vadd_dataIn(
__global int* a,
__global int* b
) {

for(int i=0; i<N; i++) {
g_var0[i]= a[i];
g_var1[i]= b[i];
}
}

//------------------------------------------------------------------------------

__kernel void __attribute__ ((reqd_work_group_size(1, 1, 1)))
vadd_cal() {

int input_data_a, input_data_b, outdata;
for (int i = 0; i < N; i++) {
input_data_a = g_var0[i];
input_data_b = g_var1[i];
outdata = input_data_a + input_data_b;
g_var2[i] = outdata;
}
}

//------------------------------------------------------------------------------

__kernel void __attribute__((reqd_work_group_size(1,1,1)))
vadd_dataOut(
__global int* c
) {
for(int i=0; i<N; i++) {
c[i]= g_var2[i];
}
}

--------------------------------------------------------------------

 

My host code is :

#include "xcl2.hpp"

#define LENGTH (10)

int main(int argc, char* argv[]) {
size_t vector_size_bytes = sizeof(int) * LENGTH;
int t = 1;
//Source Memories
std::vector<unsigned int> source_a(LENGTH);
std::vector<unsigned int> source_b(LENGTH);
std::vector<unsigned int> result_sim(LENGTH);
std::vector<unsigned int> result_krnl(LENGTH);

/* Create the test data and golden data locally */
for (int i = 0; i < LENGTH; i++) {
source_a[i] = 1;
source_b[i] = 1;
result_sim[i] = source_a[i] + source_b[i];
}

// OPENCL HOST CODE AREA START

//Getting Xilinx Platform and its device
std::vector < cl::Device > devices = xcl::get_xil_devices();
cl::Device device = devices[0];
std::string device_name = device.getInfo<CL_DEVICE_NAME>();

//Creating Context and Command Queue for selected Device
cl::Context context(device);
cl::CommandQueue q(context, device);

//Loading XCL Bin into char buffer
std::string binaryFile = xcl::find_binary_file(device_name, "vadd");
cl::Program::Binaries bins = xcl::import_binary_file(binaryFile);
devices.resize(1);
cl::Program program(context, devices, bins);

//Creating Kernel and Functor of Kernel
int err1;
cl::Kernel kernel_input(program, "vadd_dataIn", &err1);
auto krnl_in = cl::KernelFunctor<cl::Buffer&, cl::Buffer&>(kernel_input);
cl::Kernel kernel(program, "vadd_cal", &err1);
auto krnl_vadd = cl::KernelFunctor<>(kernel);
cl::Kernel kernel_output(program, "vadd_dataOut", &err1);
auto krnl_out = cl::KernelFunctor<cl::Buffer&>(kernel_output);

//Creating Buffers inside Device
cl::Buffer buffer_a(context, CL_MEM_READ_ONLY, vector_size_bytes);
cl::Buffer buffer_b(context, CL_MEM_READ_ONLY, vector_size_bytes);
cl::Buffer buffer_c(context, CL_MEM_WRITE_ONLY, vector_size_bytes);

//Copying input data to Device buffer from host memory
q.enqueueWriteBuffer(buffer_a, CL_TRUE, 0, vector_size_bytes,
source_a.data());
q.enqueueWriteBuffer(buffer_b, CL_TRUE, 0, vector_size_bytes,
source_b.data());

//Running Kernel
krnl_in(cl::EnqueueArgs(q, cl::NDRange(1, 1, 1), cl::NDRange(1, 1, 1)),
buffer_a, buffer_b);
krnl_vadd(cl::EnqueueArgs(q, cl::NDRange(1, 1, 1), cl::NDRange(1, 1, 1)));
krnl_out(cl::EnqueueArgs(q, cl::NDRange(1, 1, 1), cl::NDRange(1, 1, 1)),
buffer_c);
q.finish();

//Copying Device result data to Host memory
q.enqueueReadBuffer(buffer_c, CL_TRUE, 0, vector_size_bytes,
result_krnl.data());

// OPENCL HOST CODE AREA END

/* Compare the results of the kernel to the simulation */
bool krnl_match = true;
for (int i = 0; i < LENGTH; i++) {
if (result_sim[i] != result_krnl[i]) {
std::cout << "Error: Result mismatch" << std::endl;
std::cout << "i = " << i << " CPU result = " << result_sim[i]
<< " Krnl Result = " << result_krnl[i] << std::endl;
krnl_match = false;
break;
}
}
std::cout << "TEST " << (krnl_match ? "PASSED" : "FAILED") << std::endl;
return (krnl_match ? EXIT_SUCCESS : EXIT_FAILURE);
}

------------------------------------------------------------------

 

 

The compilation output + the error :

make -j8 incremental
/opt/Xilinx/SDx/2018.2/bin/xocc -t hw --platform zcu102 --save-temps --clkid 1 -c -k vadd_dataIn --nk vadd_dataIn:1 --messageDb vadd/vadd_dataIn.mdb -I"../src" --xp misc:solution_name=vadd_dataIn --temp_dir vadd --report_dir vadd/reports --log_dir vadd/logs -o"vadd/vadd_dataIn.xo" "../src/vadd.cl"

****** xocc v2018.2 (64-bit)
**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

Attempting to get a license: ap_opencl
WARNING: [XOCC 17-301] Failed to get a license for 'ap_opencl'. Explanation: Problem encountered while checking for license feature ap_opencl license version 2018.06. Try setting the environment variable FLEXLM_DIAGNOSTICS=3 and re-running this software to get more information.
Resolution: Check the status of your licenses in the Vivado License Manager. For debug help search Xilinx Support for "Licensing FAQ".
Attempting to get a license: ap_sdsoc
Feature available: ap_sdsoc
INFO: [XOCC 60-585] Compiling for hardware target
INFO: [XOCC 60-895] Target platform: /opt/Xilinx/SDx/2018.2/platforms/zcu102/zcu102.xpfm
INFO: [XOCC 60-423] Target device: zcu102
INFO: [XOCC 60-242] Creating kernel: 'vadd_dataIn'

===>The following messages were generated while performing high-level synthesis for kernel: vadd_dataIn Log file:/home/motebphd2019/SDx_workspace_2018.2/on-chip-global-mem-test/Debug/vadd/vadd_dataIn/vadd_dataIn/vivado_hls.log :
INFO: [XOCC 204-61] Option 'relax_ii_for_timing' is enabled, will increase II to preserve clock frequency constraints.
INFO: [XOCC 60-594] Finished kernel compilation
INFO: [XOCC 60-244] Generating system estimate report...
INFO: [XOCC 60-1092] Generated system estimate report: /home/motebphd2019/SDx_workspace_2018.2/on-chip-global-mem-test/Debug/vadd/reports/vadd_dataIn/system_estimate_vadd_dataIn.xtxt
INFO: [XOCC 60-586] Created vadd/vadd_dataIn.xo
INFO: [XOCC 60-791] Total elapsed time: 0h 0m 26s
/opt/Xilinx/SDx/2018.2/bin/xocc -t hw --platform zcu102 --save-temps --clkid 1 -c -k vadd_dataOut --nk vadd_dataOut:1 --messageDb vadd/vadd_dataOut.mdb -I"../src" --xp misc:solution_name=vadd_dataOut --temp_dir vadd --report_dir vadd/reports --log_dir vadd/logs -o"vadd/vadd_dataOut.xo" "../src/vadd.cl"

****** xocc v2018.2 (64-bit)
**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

Attempting to get a license: ap_opencl
WARNING: [XOCC 17-301] Failed to get a license for 'ap_opencl'. Explanation: Problem encountered while checking for license feature ap_opencl license version 2018.06. Try setting the environment variable FLEXLM_DIAGNOSTICS=3 and re-running this software to get more information.
Resolution: Check the status of your licenses in the Vivado License Manager. For debug help search Xilinx Support for "Licensing FAQ".
Attempting to get a license: ap_sdsoc
Feature available: ap_sdsoc
INFO: [XOCC 60-585] Compiling for hardware target
INFO: [XOCC 60-895] Target platform: /opt/Xilinx/SDx/2018.2/platforms/zcu102/zcu102.xpfm
INFO: [XOCC 60-423] Target device: zcu102
INFO: [XOCC 60-242] Creating kernel: 'vadd_dataOut'

===>The following messages were generated while performing high-level synthesis for kernel: vadd_dataOut Log file:/home/motebphd2019/SDx_workspace_2018.2/on-chip-global-mem-test/Debug/vadd/vadd_dataOut/vadd_dataOut/vivado_hls.log :
INFO: [XOCC 204-61] Option 'relax_ii_for_timing' is enabled, will increase II to preserve clock frequency constraints.
INFO: [XOCC 60-594] Finished kernel compilation
INFO: [XOCC 60-244] Generating system estimate report...
INFO: [XOCC 60-1092] Generated system estimate report: /home/motebphd2019/SDx_workspace_2018.2/on-chip-global-mem-test/Debug/vadd/reports/vadd_dataOut/system_estimate_vadd_dataOut.xtxt
INFO: [XOCC 60-586] Created vadd/vadd_dataOut.xo
INFO: [XOCC 60-791] Total elapsed time: 0h 0m 24s
/opt/Xilinx/SDx/2018.2/bin/xocc -t hw --platform zcu102 --save-temps --clkid 1 -c -k vadd_cal --nk vadd_cal:1 --messageDb vadd/vadd_cal.mdb -I"../src" --xp misc:solution_name=vadd_cal --temp_dir vadd --report_dir vadd/reports --log_dir vadd/logs -o"vadd/vadd_cal.xo" "../src/vadd.cl"

****** xocc v2018.2 (64-bit)
**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

Attempting to get a license: ap_opencl
WARNING: [XOCC 17-301] Failed to get a license for 'ap_opencl'. Explanation: Problem encountered while checking for license feature ap_opencl license version 2018.06. Try setting the environment variable FLEXLM_DIAGNOSTICS=3 and re-running this software to get more information.
Resolution: Check the status of your licenses in the Vivado License Manager. For debug help search Xilinx Support for "Licensing FAQ".
Attempting to get a license: ap_sdsoc
Feature available: ap_sdsoc
INFO: [XOCC 60-585] Compiling for hardware target
INFO: [XOCC 60-895] Target platform: /opt/Xilinx/SDx/2018.2/platforms/zcu102/zcu102.xpfm
INFO: [XOCC 60-423] Target device: zcu102
INFO: [XOCC 60-242] Creating kernel: 'vadd_cal'

===>The following messages were generated while performing high-level synthesis for kernel: vadd_cal Log file:/home/motebphd2019/SDx_workspace_2018.2/on-chip-global-mem-test/Debug/vadd/vadd_cal/vadd_cal/vivado_hls.log :
INFO: [XOCC 204-61] Option 'relax_ii_for_timing' is enabled, will increase II to preserve clock frequency constraints.
INFO: [XOCC 60-594] Finished kernel compilation
INFO: [XOCC 60-244] Generating system estimate report...
INFO: [XOCC 60-1092] Generated system estimate report: /home/motebphd2019/SDx_workspace_2018.2/on-chip-global-mem-test/Debug/vadd/reports/vadd_cal/system_estimate_vadd_cal.xtxt
INFO: [XOCC 60-586] Created vadd/vadd_cal.xo
INFO: [XOCC 60-791] Total elapsed time: 0h 0m 26s
/opt/Xilinx/SDx/2018.2/bin/xocc -t hw --platform zcu102 --save-temps --clkid 1 -l --nk vadd_dataIn:1 --nk vadd_dataOut:1 --nk vadd_cal:1 --messageDb vadd.mdb --xp misc:solution_name=link --temp_dir vadd --report_dir vadd/reports --log_dir vadd/logs --remote_ip_cache /home/motebphd2019/SDx_workspace_2018.2/ip_cache -o"vadd.xclbin" vadd/vadd_dataIn.xo vadd/vadd_dataOut.xo vadd/vadd_cal.xo --sys_config ocl

****** xocc v2018.2 (64-bit)
**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

INFO: [XOCC 60-629] Linking for hardware target
INFO: [XOCC 60-895] Target platform: /opt/Xilinx/SDx/2018.2/platforms/zcu102/zcu102.xpfm
INFO: [XOCC 60-423] Target device: zcu102
INFO: [XOCC 60-825] xocc command line options for sdx_link are --xo vadd/vadd_dataIn.xo --xo vadd/vadd_dataOut.xo --xo vadd/vadd_cal.xo --nk vadd_dataIn:1 --nk vadd_dataOut:1 --nk vadd_cal:1 -clkid 1 -keep
using /opt/Xilinx/SDx/2018.2/platforms/zcu102/zcu102.xpfm
extracting xo v3 file /home/motebphd2019/SDx_workspace_2018.2/on-chip-global-mem-test/Debug/vadd/vadd_dataIn.xo
ERROR: [KernelCheck 83-113] Kernel 'vadd_dataIn' accesses non-pipe global variable 'xcl_mem_g_var0', which is not supported.

Error generating intermediate file /home/motebphd2019/SDx_workspace_2018.2/on-chip-global-mem-test/Debug/vadd/link/sys_link/iprepo/temp/xo0/ip_repo/xilinx_com_hls_vadd_dataIn_1_0/vadd_dataIn.fcnmap.xml
Error: unable to create function map for HLS kernel vadd_dataIn
Unable to process /home/motebphd2019/SDx_workspace_2018.2/on-chip-global-mem-test/Debug/vadd/vadd_dataIn.xo
Error processing .xo files, exiting
ERROR: [XOCC 60-398] sdx_link failed
ERROR: [XOCC 60-626] Kernel link failed to complete
ERROR: [XOCC 60-703] Failed to finish linking
makefile:94: recipe for target 'vadd.xclbin' failed
make: *** [vadd.xclbin] Error 1

 

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