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Adventurer
Adventurer
626 Views
Registered: ‎02-28-2015

opencl pipe linking stage error

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Hi guys,

I am working on some OpenCL kernel which has pipe.

I have only below lines relative to the pipe implementation

1. pipe long k6_outVal __attribute__((xcl_reqd_pipe_depth(240*135)));

2. __kernel write_kernel (<has-some-inputs-outputs>)

{

long x1 = 0;

x1 = <do-some-operation>;

 write_pipe_block(k6_outVal, &x1);

}

3. __kernel read_kernel (_global long * restrict outVal, <has-some-inputs-outputs>)

{

int id6 = <do-some-operation>;

read_pipe_block(k6_outVal, &outVal[id6]);

}

 

compilation stage (xocc -c) is running correctly but there is error as follow in linking stage (xocc -l).

Kernel Specs:
ERROR: [CFGEN 83-1392] Illegal port name 'k6_outval_pipe' for comp 'process_data_slice6'
ERROR: [CFGEN 83-1307] getPort(k6_outval_pipe, process_data_slice6) is null
ERROR: [CFGEN 83-1316] Failed request for port named k6_outval_pipe in xd:component type process_data_slice6
/opt/Xilinx/SDx/2017.4.op/bin/cfgen: line 15:  9668 Segmentation fault      (core dumped) ${BIN_DIR}/unwrapped/lnx64.o/`basename ${LOADER}` $@
Error generating design file for apsys_0.xml
command: /opt/Xilinx/SDx/2017.4.op/bin/cfgen    -r <my_path>/work/_sds/.cdb/xd_ip_db.xml -o apsys_0.xml
Error creating intermediate design file, exiting
ERROR: [XOCC 60-398] sdx_link failed
ERROR: [XOCC 60-626] Kernel link failed to complete
ERROR: [XOCC 60-703] Failed to finish linking
make: *** [xclbin/kernelcode.hw.xilinx_aws-vu9p-f1-04261818_dynamic_5_0.xclbin] Error 1

 

1. does anyone have familiar with above error at linking stage ?

2. Where can I find the "getPort(k6_outval_pipe, process_data_slice6)" function ?

*please note that there is no named like "k6_outval_pipe" in my openCL kernel

*my kernel name is "process_data_slice6" as mentioned in above.

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1 Solution

Accepted Solutions
Adventurer
Adventurer
538 Views
Registered: ‎02-28-2015

Re: opencl pipe linking stage error

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Hi @brucey

I was able to find out the issue for the above error. it is due to uppercase letter in pipe variable.

I referred the UG1238, pg15

Anyway thanks your help in xcl_reqd_pipe_depth.

Thank You

View solution in original post

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3 Replies
Xilinx Employee
Xilinx Employee
590 Views
Registered: ‎03-24-2010

Re: opencl pipe linking stage error

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Please try valid pipe depth:

Valid depth values are 16, 32, 64, 128, 256, 512, 1024,
2048, 4096, 8192, 16384, 32768.

 

Refer to xcl_reqd_pipe_depth command in UG1253.

Regards,
brucey
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Adventurer
Adventurer
575 Views
Registered: ‎02-28-2015

Re: opencl pipe linking stage error

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Hi @brucey

Thanks for your reply,

I have changed the xcl_reqd_pipe_depth to 32768, but it gave me the same above error.

 

What can be the other possible reasons for above error?

Where can I find the getPort() function? (any file created in xocc -c operation, like .v, .c, .h ???)

 

Thank You

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Adventurer
Adventurer
539 Views
Registered: ‎02-28-2015

Re: opencl pipe linking stage error

Jump to solution

Hi @brucey

I was able to find out the issue for the above error. it is due to uppercase letter in pipe variable.

I referred the UG1238, pg15

Anyway thanks your help in xcl_reqd_pipe_depth.

Thank You

View solution in original post

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