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Adventurer
Adventurer
8,142 Views
Registered: ‎02-22-2016

2015.1 export hardware problem

Hi everybody, 

I'm using Vivado 2015.1 and AC701 board, in my peoject I want to use Internal logic analyzer. I have followed this document step by step .

https://www.so-logic.net/documents/knowledge/tutorial/Basic_ESD_Tutorial/sec3.html

When I got to the step 20, I got a warning that  

the hardware handoff file(.sysdef) does not exist. It may not have generated because

1. Bistream might not have generated. Generate bitstream and export otherwise do not include bitstream in export.

2.there are no IPI design hardware handoff files. Check the log messages for more details

 

To solve this problem I have seen a recommendation  and  tried the TCL commands.

Code:
set PROJECT_NAME "my_project"
set TOPLEVEL_NAME "toplevel"

write_hwdef -force -file ./$PROJECT_NAME.runs/synth_1/$TOPLEVEL_NAME.hwdef

write_sysdef -force -hwdef ./$PROJECT_NAME.runs/synth_1/$TOPLEVEL_NAME.hwdef -bitfile ./$PROJECT_NAME.runs/impl_1/$TOPLEVEL_NAME.bit -file ./$PROJECT_NAME.runs/impl_1/$TOPLEVEL_NAME.sysdef

When I run the 'write_hwdef' command I get the error message that -
write_hwdef -force -file ./mb_mcs_core.runs/synth_1/mb_mcs_core.hwdef
INFO: [Vivado_Tcl 4-424] Cannot write hardware definition file as there are no IPI block design hardware handoff files present

 

how can I solve this problem?

Thank you in advence,

herdinc

 

Note: ı have not designed my project with the ip integrator. I have only used uartlite ip and write suitable code to transmit a word. In this example the debug process is done with the ip integrator menu bar.

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4 Replies
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Xilinx Employee
Xilinx Employee
7,851 Views
Registered: ‎08-02-2007

hi,

 

>>>>>   Note: ı have not designed my project with the ip integrator. I have only used uartlite ip and write suitable code to transmit a word. In this example the debug process is done with the ip integrator menu bar.

 

can you share the block diagram of your design? Is your requirement to debug uartlite IP without having a microblaze?

 

--hs

 

 

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Adventurer
Adventurer
7,809 Views
Registered: ‎02-22-2016

Hi @htsvn

I have just UARTlite block in my design.I want to visualize only tx signal.

Thank you,

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Newbie
Newbie
7,767 Views
Registered: ‎05-08-2016

I am also experiencing the exact same problem as @herdinc.  I also tried the same TCL suggestion and got the same error message: 

INFO: [Vivado_Tcl 4-424] Cannot write hardware definition file as there are no IPI block design hardware handoff files present

 

Did anyone figure out a solution? @htsvn?

I have attached my block design if that is at all helpful.

 

Thanks in advance!

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Xilinx Employee
Xilinx Employee
7,750 Views
Registered: ‎08-02-2007

hi,

 

the procedure mentioned in the link is trying to debug the design which is a part of an Embedded sub-system. looking at your requirement it looks that you have a UART peripheral only. In this case, you need not export hardware for software application creation. To debug just the IP, you can refer the tutorial as mentioned here

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_4/ug936-vivado-tutorial-programming-debugging.pdf

 

--hs

 

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