10-10-2019 08:04 AM
I have a Virtex 7 project that builds successfully and passes timing. When I add a debug core the project finishes implementation with the error "Failed Timing and Nets". When I look at the problem net properties, it says it is routable but not routed. I tried to route this using the TCL command but it does not solve the issue.
I tried to upload the zipped project, but it is evidently too large. Is there a subset of project that I can upload for review?
I am using Vivado version 14.4, and unfortunately do not have the time to update the project to the latest version of Vivado.
If someone can point me in the right direction, it would be much appreciated.
10-10-2019 08:10 AM
Heisenberg uncertainty principle... to observe something you have to, somehow, alter what you observe. Therefore, what you observe is not exactly what you wanted to observe without disturbing it.
Sorry for the philosophy. what happens is, simply, you added something in the silicon and Vivado can't find a way to meet the timing constraints...
What you can do, if it's for debug purposes, lower your clock and relax your timing conditions
10-10-2019 08:14 AM
Wow, thats going back 20 plus versions of Vivado..
Typiclay I see people
a) not using the same clock to clock the ILA as the design they are trying to sample
b) connect to an IO pin, the ILA has no access to pins of th echip, only internal signals.
To solve the second, change where your connecting to ,
to solve the first, change the clocking of the ILA
If you have pure timming problems,
try using a smaller ILA width, and / or putting register buffering of the signals you want to monitor.
10-10-2019 08:28 AM
This design is one of many circuit cards in a larger system. Unfortuantely, the debugging I need to do is "in-system" I can't arbitrarily change my clock without breaking necessary functions between system components.
I was hoping to get some tips on things to look into with the FPGA architecture to solve my issue.
10-10-2019 08:32 AM
its th eclock of th elogic analyser you rinstnatiating that shoudl eb the same as th esignlas your trying to look at.
if you are looking at signals on multiple clock domains, then either use multiple ILAs , one on each of the clock domains you want to look at ( but think about how your going to trigger the ILAs )
or add some clock crossing logic to get the data into the single ILA.
10-10-2019 09:16 AM
I took a look at the ILA core, and it is using the same clock. However, the dbg_hub that drives the SL_IPORT net to the ILA uses a differenct clock. Is this an issue?
The nets I am looking at are not attached to pins, at this point I am just trying to get a simple debug core successfully inserted. I am connecting the ILA to internal nets that drive a status register used by software through a microblaze. I am loking at a 16 bit value, but will try using just a single bit (I beleive I went this route before, so have a suspicion this will still fail).
I tried adding Input pipe stages in the Setup Debug GUI, I'm assuming this is the same as adding buffers to my nets in front of the ILA?
Thanks for your help here.
10-10-2019 09:20 AM
I have never tried th econtroler and the ILA on different clocks,
well found, put them bothon the same clock.
By pipe lining , I mena registering to the sam eclock the ILA is running on,
for such a small ILA that shoudl not be required but I tend to put in as normal practice, gives the tools more chance of meeting timming and the ILA not changing the timming of the rest of the design.
10-10-2019 12:07 PM
Ok, I tried creating a debug core with only one net. It uses the same clock as the ILA. The project still fails with the same error. I am using the "Set up Debug" option in the syntheszed design to set up the Debug Core.
The dbg_hub uses a different clock than the ILA, but I don't see where I can specify to change this clock in Vivado. I am choosing the correct clock for my net in the "Setup Debug" GUI.
Can anyone tell me:
1) How to change the dbg_hub clock to the same used by the ILA?
2) Is the fact they have different clocks definitely an issue?
10-10-2019 12:20 PM
10-18-2019 01:47 PM
What were the nets that could not be routed? re they ILA related? Could you paste a screenshot of the errors that you get (probably after running the implementation)? Do you see any other Error or Critical Warnings? If so, could you post those too?
Also, what is the utilization rate of your device? If it's pretty full, Vivado might be having a hard time in finding extra space and memory to add the ILA.
Did adding the pipe stages to the ILA did not help? That is one of the techniques to flexibilize timing propagation to the ILA and facilitate routing.
It's not really a problem that your dbg_hub is using a different clock than the ILA, but you can change it with the following constraint (you have to run TCL command before starting the Implementation process):
disconnect_debug_port dbg_hub/clk connect_debug_port dbg_hub/clk [get_nets <net name of the clk signal of interest>]
I don't think that will solve your problem, though. It looks more like a place & route issue. Looking at the error and warning messages, I might be able to have a better idea.