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jt94096
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Registered: ‎09-21-2018

All ILAs undetected if a single ILA clock is not toggling (Zynq US+ MPSoC using Vitis/Vivado 2020.1 or 2020.2)

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Hello,

I am using a Zynq US+ MPSoC with a simple test design that has several ILAs to monitor inbound and outbound data. I have discovered that if the clock to any ILA is not toggling then Vivado Hardware Manager does not detect *ANY* of the ILAs even if the others have a valid clock. If I connect a valid clock to the one ILA that was connected to a non-toggling clock then all ILAs are detected. I have seen this behavior in Vitis/Vivado 2020.1 and 2020.2, have not tried it with 2019.x but never had this problem with 2018.3.

Now that I have figured this out it is no longer blocking me but I just wanted to report it. Is there any way I could be doing something else to cause this?

Thanks - Jason

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anunesgu
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Registered: ‎02-09-2017

Hi @jt94096,

Since you've mentioned that the issue has been solved, would you mind sharing what you did? Or did you fix it by providing a valid clock to all the ILAs?

I'd expect only the ILA that doesn't have a valid clock to stop working.

One point to be aware is that the Debug Hub (which is a hub to collect the data from all the debug cores) uses the same clock as one of the ILAs in the design. I you open your synthesized design, you should be able to see which clock is being used for the dbg_hub block. This clock is automatically picked by Vivado, so it could be that the same invalid ILA clock has also been picked to be the dbg_hub clock, in which case all the ILAs would not work.

Thank you,

Andre Guerrero

Product Applications Engineer

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anunesgu
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Moderator
659 Views
Registered: ‎02-09-2017

Hi @jt94096,

Since you've mentioned that the issue has been solved, would you mind sharing what you did? Or did you fix it by providing a valid clock to all the ILAs?

I'd expect only the ILA that doesn't have a valid clock to stop working.

One point to be aware is that the Debug Hub (which is a hub to collect the data from all the debug cores) uses the same clock as one of the ILAs in the design. I you open your synthesized design, you should be able to see which clock is being used for the dbg_hub block. This clock is automatically picked by Vivado, so it could be that the same invalid ILA clock has also been picked to be the dbg_hub clock, in which case all the ILAs would not work.

Thank you,

Andre Guerrero

Product Applications Engineer

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jt94096
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Registered: ‎09-21-2018

When I went to reply I clicked on 'accepted as solution' by accident, but your response is on-target and likely the correct diagnosis. Yes, I fixed the problem by connecting a different clock to the ILA that was using a non-toggling clock (at which point all ILAs were using an active clock). I will try changing it back and will let you know if Vivado picks that clock for the debug hub.

Jason

jt94096
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Registered: ‎09-21-2018

I changed the design to use an inactive clock for one ILA and the schematic shows that Vivado picked a valid clock. The design has gone through a few stages of changes since I had the problem so this doesn't disprove the accepted solution. Just wanted to provide this feedback. FYI I found this related thread that explains how to specify which clock to use for the debug hub:

https://forums.xilinx.com/t5/Synthesis/about-xilinx-debug-hub-clock/m-p/886686

 

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