cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
marrud
Visitor
Visitor
292 Views
Registered: ‎03-12-2021

All dynamic power removed when using SAIF file for power report

Greetings,

I am looking into various design possibilities for creating a low power SPI master to see what design choices who affects the power consumption in the system. To look into this, I have a SPI master and slave in verilog and have made a testbench in Vivado where I simulate some typical behavior. This is a rather small testbench where I only sent 2 bytes of data between the devices.

The issue I am having is with the power report. I am using the implemented design of the master together with SAIF files generated both from behavioral and post-implementation timing/functional simulation to generate the report. The more of the systems behavior I constrain, the less dynamical power consumption I get. So with the power report with the behavioral SAIF, I get 59% dynamic power, but with the SAIF from the post-implementation simulations, I get ~7% dyn power. When applying a clock constrain the dyn power drops to <1%. 

Since my project is the reduce the dynamical power in the design, it is a problem if the report say that it barely is any dyn power at all even before I have made modifications. I therefore wonder if these results I see are normal behavior or if I have done something wrong. Since this is a part of a master thesis I am still quite new to this type of work and Vivado, so if there is some better ways of checking the power consumption of a design based on the data in the system, I would be very grateful for some tips. The desired result is to be able to find the required energy per transmitted bit for the different designs.

 

0 Kudos
2 Replies
tenzinc
Moderator
Moderator
186 Views
Registered: ‎09-18-2014

Can you share your DCP? What is your device/resource utilization look like? Generally I expect the dynamic power to reduce as more power related constraints are specified into vivado especially for a small design. Even more so on a larger FPGA with higher static power consumption. 

 

Regards,

T



Don’t forget to reply, kudo, and accept as solution.

Get started FAST with our UltraFAST design methodoly guides and don't forget to visit our Xilinx Design Hubs for additional resources and reference.

If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs

------------------------------------------------------------------------------------------------

0 Kudos
marrud
Visitor
Visitor
160 Views
Registered: ‎03-12-2021

Thank for the reply. Apparently I was not allowed to upload the .dcp file up to this forum so I have uploaded a print of the design instead. If needed I can try to find some other way to upload the .dcp file or if you know how I can go around this error (see attachment). I have also uploaded the utilization and power reports. I changed some settings of the power report so it is displayed in mW and then I see some dynamic power in the range of 0.100-0.500 mW depending on modifications in the simulation/constraints. Due to the small size of this design I have now thought that this might be the correct size of the dynamic power, but maybe you can tell if this is a correct assumption or not?

I have a static power of ~104 mW and I use a Zynq-7000 FPGA. Do you know if this reported consumption is the static consumption only for my specific design, or if this number includes the static power consumed by powering the FPGA?

 

Best regards

Markus

dcpError.png
0 Kudos