11-03-2020 06:19 AM
We have designed a video Ethernet board (Gb Ethernet) based on XC7A35T and XC7A50T. The current design uses XC7A50T CSG324.
We are facing a power issue. With no bitsream loaded, the board consumes 0.9W. When we load the bitstream the board consumes 3.8W and the internal temperature reaches 88°C (measured with XADC).
All power rails are OK (3.3V/1.8V/1.0V/1.5V)
The design includes a DDR3 controller @ 333Mhz, a triple speed Ethernet MAC and custom logic.
Everything works correctly except that the board is getting very hot!
The FPGA utilization is about 60% and the power estimation is 1.115W with a jonction temperature of 30.3°C
We have already checked the schematics and we observe the same behaviour with board equiped with XC7A35T and XC7A50T.
11-03-2020 06:43 AM
The power estimation tool makes assumptions about switching activity, airflow and a heatsink. Did you provide switching estimates, possibly from a simulation to override the default switching estimates? Does your board have the airflow and heatsink that the power estimation tool assumes? Did you take into account that other components on the board will draw more power if the FPGA is active, specifically the DDR3, but probably other components too?
11-03-2020 06:48 AM
The 324 package is very small, so it doesn't surprise me it gets to 80C with a Gig Ethernet. 10 GbE I suppose.
What surprises me is that the power estimator guessed you 1W. My take is that something is missing there. If the board is dense, other hot spots (dcdc converters, etc) may "help" keeping the FPGA hot, if you have a thermal camera you can easily check that.
Other things to double check are pull-ups, terminations, any differential signal meant to be connected via DC-blocking series capacitor, etc.
11-03-2020 08:02 AM
Ethernet speed is 1Gbps only (not 10G).
For DDR3 and IODELAY we use two clocks, one at 333Mhz and one at 200Mhz.
These are LVDS clocks connected to 1.5V banks so they are AC coupled.
I have attached the related schematics.
11-03-2020 10:08 AM
The above is fine, that won't dissipate that much.
What power estimator do you mean, the excel spreadsheet Xilinx provides where you fill the details or the result from Vivado after implementation? The latter should be quite accurate.
11-03-2020 01:38 PM
Vivado after implementation.
With following settings: no airflow, no heatsink, 4pf load, smal board, 8 to 11 layers we get 1.124W
In the design most of the consumption comes from the PHY of the DDR3 controller.
11-03-2020 05:15 PM
Does the power estimation tool have an accurate estimate of switching rates? What else on the board uses power? The DDR3 will. Do you have any DC/DC converters? If they are 60% efficient, how much heat are they dissipating? Any linear regulators? If your board is getting hot from other components, it won't dissipate as much heat from the FPGA. @joancab 's advice is good. Get a infrared thermometer or camera and check all components. If you can't reduce current draw, you must find a way to get rid of some heat. A heatsink, airflow, a thermal pad to the chassis, something like that.
11-03-2020 09:50 PM
The toggle rate is set to its default value 12.5.
I Will check with a thermal camera but the hotter chip is the FPGA.
When everything is in reset state (FPGA Ethernet phy ddr3...) the board consumption is about 2W (0.9W without bitstream loaded).
11-04-2020 01:16 AM
"When everything is in reset state (FPGA Ethernet phy ddr3...) the board consumption is about 2W (0.9W without bitstream loaded)"
That makes me suspect there is something wrong with the DDR
11-04-2020 02:24 AM
I agree with you. Here is our configuration:
I have attache the schematics of the DDR3.
11-04-2020 03:05 AM - edited 11-04-2020 03:08 AM
Could it be you have there the 'L' part for 1V35 and you are supplying it with 1V5?
If the DDR clamps the inputs, even if powered at 1V5, then there would be a voltage mismatch between the FPGA and the DDR that would inevitably be dissipated somewhere
11-04-2020 04:53 AM
Are the DDR and/ or GbE PHY chips hot as well or just the FPGA?
Could you tweak the design to disable either the Ethernet and the DDR to see if one of these (or none or both) are the culprit?
11-04-2020 05:19 AM
We have monitored temperature with a thermal camera, the FPGA is clearly the hotter.
We have another board based on the same design (FPGA + DDR3) but without Ethernet that seems to present the same behaviour.
This board has the same FPGA (XC7A35T and same DDR3 memory); the internal logic is different.
11-04-2020 05:24 AM
Is the ddr phy generated with MIG? I would double check it, typically pins are swapped when routing the board so the IP needs to change accordingly, could that have happened?
11-06-2020 08:01 AM
I measured the consumption at different levels:
Evrything works correctly. On the board we use 3.3V (IO), 1.5V (DDR3), 1.0V (Core), 1.8V (VCCAUX)