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Participant sean.durkin
Participant
9,284 Views
Registered: ‎05-15-2013

BUG: Programming/debugging broken since Vivado 2013.4 for JTAG-chains witj non-XIlinx devices

Hi *,

 

I just upgraded to Vivado 2013.4 and now I can't program bitfiles or do any debugging in "Hardware Manager" anymore.

 

On my board, there's a microcontroller in the JTAG-chain after the FPGA, so I have to configure it's IR_LENGTH.

This has worked without problems in Vivado 2013.2/3, but since upgrading to 2013.4, every operation fails with a message about the DONE-pin being low (which it is not). Downloading a bitfile does not work, either. Programming does not even start but I immediately get the the "DONE pin is low" message. It looks like it does not even start downloading configuration data to the FPGA. But it does scan the JTAG chain and lists all devices with their correct IDs.

 

Programming does work on the AC701, so I suspect that Vivado 2013.4 has problems with my setup with a non-Xilinx device in the JTAG chain (which wasn't a problem up until now). Maybe it doesn't honor the IR_LENGTH-setting anymore or something... There are no error or warning messages that could help track down the problem, not even if I run everything with the "-verbose" option.

 

I tried this on 4 different workstations (all Windows) and with several platform cables, the problem is the same in all cases, so I can rule out that this is just an issue of my installation. Re-installing 2013.4 didn't help, either. Changing the JTAG frequency makes no difference as well (in Vivado 2013.3, I can run everything at 12MHz without any problems).

 

This is NOT a hardware issue, so please don't advise me on any "DONE did not go HIGH" problems (DONE IS high, the FPGA is programmed successfully, but it looks like JTAG access does not work, hence reading FPGA status returns garbage). This is a pure software problem with 2013.4. All my boards work perfectly well with iMPACT and all Vivado releases prior to 2013.4.

 

I've attached a console logs for 2013.4 and 2013.3. In both cases, the same hardware and the same commands are used. In both cases, the FPGA is already configured via SPI and DONE is high.

 

Is anyone else seeing this? Is there a workaround? Secret debug modes I could turn on to supply more information? In the meantime I'm sticking to 2013.3...

 

Greetings,

Sean

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