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Visitor
Visitor
9,356 Views
Registered: ‎03-22-2015

Beginner Debug ?...Forcing input HI

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Hi

I seem to have got though simulation and some of the debug of my first project.   With the debug items that use the clock I get the debug output I would expect.  But want to force a marked debug signal HI so I can check if I am latching it in my block.  I can not find any refences how this is done.

 

Attached is a image of the circuit.  If you have any suggestions or questions please let me know...Thanks

 

Gus50310

Debug force input HI.jpg
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Xilinx Employee
Xilinx Employee
17,542 Views
Registered: ‎04-16-2012

Hello @gus50310

 

The suggestion is to use VIO core for providing the inputs to the design.

Check this product guide of VIO core: http://www.xilinx.com/support/documentation/ip_documentation/vio/v3_0/pg159-vio.pdf

 

Thanks,

Vinay

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Visitor
Visitor
9,349 Views
Registered: ‎03-22-2015

I suppose I should have indicated I am using the Vivado 2015.3 tool set

Gus50310

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Xilinx Employee
Xilinx Employee
17,543 Views
Registered: ‎04-16-2012

Hello @gus50310

 

The suggestion is to use VIO core for providing the inputs to the design.

Check this product guide of VIO core: http://www.xilinx.com/support/documentation/ip_documentation/vio/v3_0/pg159-vio.pdf

 

Thanks,

Vinay

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Moderator
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Registered: ‎01-16-2013
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Visitor
Visitor
9,152 Views
Registered: ‎03-22-2015

Hi vappala

Thanks for the reply.  I just have not had a chance to check it out yet.

Thanks....Gus50310

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Visitor
Visitor
9,151 Views
Registered: ‎03-22-2015

Hi yashp

Thanks for the reply.  I just have not had a chance to check it out yet.

Thanks....Gus50310

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Moderator
Moderator
9,141 Views
Registered: ‎07-01-2015

Hi @gus50310,

 

Please go through Lab-3 of following link to get more information on using VIO core
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_2/ug936-vivado-tutorial-programming-debugging.pdf

 

Please let us know the outcomes after trying the above suggestions. Also let us know if you are facing any issues with the flow.

 

Thanks,
Arpan

Thanks,
Arpan
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Visitor
Visitor
8,944 Views
Registered: ‎03-22-2015

HI vuppula - yashp - arpansur

After gathering the infromation I gleaned from looking at all the suggestions I believe I have the debug setup using the VIO IPs to confirm the logic is working the way I want.

Thanks....Gus50310

 
Capture.JPG
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