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creedxlnx
Adventurer
Adventurer
10,812 Views
Registered: ‎09-30-2015

Bitgen Error NSTD-1 and UCIO-1

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I am running Vivado 2015.1 and trying to generate a bitfile.  I have the following lines in my .xdc:

 

set_property PACKAGE_PIN K24 [get_ports {dsurx        }]
set_property IOSTANDARD LVCMOS25 [get_ports {dsurx      }]
set_property PACKAGE_PIN K23 [get_ports {dsurtsn      }]
set_property IOSTANDARD LVCMOS25 [get_ports {dsurtsn    }]
set_property PACKAGE_PIN M19 [get_ports {dsutx        }]
set_property IOSTANDARD LVCMOS25 [get_ports {dsutx      }]
set_property PACKAGE_PIN L27 [get_ports {dsuctsn      }]
set_property IOSTANDARD LVCMOS25 [get_ports {dsuctsn    }]

 

When I run bitgen, I get the following error:

ERROR: [DRC 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 4 out of 7 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: dsuctsn, dsurx, dsurtsn, dsutx.


ERROR: [DRC 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 4 out of 7 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: dsuctsn, dsurx, dsurtsn, dsutx.

 

The other 3 ports on my design are clk200p, clk200n and reset.

 

Regards,

 

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creedxlnx
Adventurer
Adventurer
19,376 Views
Registered: ‎09-30-2015

Turns out the fix for this was a good night of sleep and a cup of coffe (it was user error).

Once I edited the constraint file that is used by THIS project, everything worked as

expected.  My apologies taking up your time.

 

Regards,

View solution in original post

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7 Replies
aher
Xilinx Employee
Xilinx Employee
10,780 Views
Registered: ‎07-21-2014
Hi,

Please constraint clock and reset signal as well. that is why you are facing this error.

-Shreyas
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vemulad
Xilinx Employee
Xilinx Employee
10,772 Views
Registered: ‎09-20-2012

Hi @creedxlnx

 

Open synthesized design and run the below command from TCL console and see if it returns any warning.

 

set_property PACKAGE_PIN K24 [get_ports {dsurx        }]

 

If tool returns warning message then remove spaces after dsurx in the above constraint and see if it helps.

 

Thanks,

Deepika.

Thanks,
Deepika.
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pratham
Scholar
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10,757 Views
Registered: ‎06-05-2013

@creedxlnx Do you have same spaces for clk200p, clk200n and reset? These ports have been constraint correctly.  If no then remove those spaces, if yes then check these ports by opening synthesized design and running those constraints.

 

What is the device are you using?

-Pratham

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creedxlnx
Adventurer
Adventurer
19,377 Views
Registered: ‎09-30-2015

Turns out the fix for this was a good night of sleep and a cup of coffe (it was user error).

Once I edited the constraint file that is used by THIS project, everything worked as

expected.  My apologies taking up your time.

 

Regards,

View solution in original post

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pratham
Scholar
Scholar
10,742 Views
Registered: ‎06-05-2013

@creedxlnx Glad to know. Please close this thread.

-Pratham

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creedxlnx
Adventurer
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10,726 Views
Registered: ‎09-30-2015

A newbie question: How do  close a thread?  I've never done it before and I don't see the option to do so as a

message option or a a topic option. 

 

Thanks,

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vemulad
Xilinx Employee
Xilinx Employee
10,723 Views
Registered: ‎09-20-2012

Hi @creedxlnx

 

After you login, you will see "accept as solution" button to the right side as shown below. Choose this option for the post which helped you.

 

Capture.PNG

 

Thanks,

Deepika.

Thanks,
Deepika.
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Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
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