Bus Plot in ChipScope

[olufola]

Hi All,

I want to view a group of signals as a bus in ChipScope. These signals are available as individual waveforms but were not loaded into the Bus Selection pane in the Bus Plot. The problem is illustrated below:

Question: How to populate the Bus Plot with signals from the Waveform window?

[gszakacs · Accepted solution]

You first need to create a bus from the loose signals.  Select multiple signals and

then right-click --> add to bus... --> new bus (this is from memory so it might be off

slightly).  The new bus name is auto-filled with one of the signal names (usually).

You may find that you need to reverse the bit order to see the bus value correctly

when done.

[olufola]

Thanks Gszakacs,

There is a ruler on top of the Waveform window along the x-axis (illustrated below). Please how can I know the unit of those numbers and can it be changed? I think its a time measurement but is it in ns? ps? micro-second or something?  Knowing the actual time interval between the very narrow pulses in the topmost waveform in the picture below is critical for my work. The problem is illustrated below:

Thanks.

[gszakacs]

ChipScope is a logic analyzer, not an oscilloscope.  The units on the "time" axis are clock periods

and depend on the clock you provided to ChipScope when you hooked up the ILA.  One tick is

one clock cycle.  So the time unit is the clock period.  ChipScope itself has no way of knowing

how fast the clock is running, so it doesn't label the axis in time units.

[ninjamafiakhan3]

---

@olufola wrote:

Thanks Gszakacs,

There is a ruler on top of the Waveform window along the x-axis (illustrated below). Please how can I know the unit of those numbers and can it be changed? I think its a time measurement but is it in ns? ps? micro-second or something?  Knowing the actual time interval between the very narrow pulses in the topmost waveform in the picture below is critical for my work. The problem is illustrated below:

Thanks.

---

In addition to the reply already given to your question, the difference from one discrete time sample to the next will be equal to the period of the clock connected to the ILA only if your storage qualifier is a condition which is equivalent to one storage qualification per period of the ILA clock (rising or falling edge etc.) for the entire length of the capture window. Since by default it is, and you probably haven't changed it, in your case it probably is equal to one period. If you use, lets say the rising edge of a slower signal (which may be periodic or not) or some other condition as a storage qualifier, the time difference between two discrete samples will not be equal to one time period.

[olufola]

Excellent one Gabor!

That completely answers my question with some bonuses added! You should probably become a college Professor. 

Thank you very much.

[olufola]

Thank you Ninja-Mafia-Khan3,

The extra explanation is very much appreciated. No Xilinx FPGA problem can withstand the assault of a Ninja and Mafia combined!

[ninjamafiakhan3]

---

@olufola wrote:

Thank you Ninja-Mafia-Khan3,

The extra explanation is very much appreciated. No Xilinx FPGA problem can withstand the assault of a Ninja and Mafia combined!

---

Haha. I wish what you said was true!

[olufola]

---

@ninjamafiakhan3 wrote:

---

@olufola wrote:

Thank you Ninja-Mafia-Khan3,

The extra explanation is very much appreciated. No Xilinx FPGA problem can withstand the assault of a Ninja and Mafia combined!

---

Haha. I wish what you said was true!

---

All you need to make it true is to add the only missing element in your name. I can bet that Ninja-Mafia-Samurai-Khan3 will solve all Xilinx FPGA problems.