12-15-2011 12:07 AM
Hello at everybody
I'm using chip scope pro analyzer for debugging my fpga (virtex 6 on ML605).
I used chipscope Pro Insert (ILA) to test my project. At first I used a clock situated on the board and it's ok. Then I replaced this clock with an exernal differential clock (by sma connectors). I allocated the IBUFGDS primitive to drive differtential clock. When I define connections in cdc file I don't find the clock single ended signal (output of IBFGDS) to make the connection. I see only the differential clock inputs but the clock has only one port to connect it. How can I do?
Thanks a lot for the answer.
12-15-2011 05:01 AM
if nothing is connected to the differential input (apart from the ChipScope that you want to connect) then the diff. buffer has been optimised out in synthesis.
In order to avoid that you can set a keep-attribute on the output-net of the ibufds. This will prevent synthesis from removing it and you can connect to that with the inserter.
signal my_clk: std_logic;
attribute keep: string;
attribute keep of my_clk: signal is "True";
diff_clk:ibufds port map(
I => CLK_P,
IB => CLK_N,
O => my_clk);
12-15-2011 06:48 AM
Thanks a lot now it works :)
I have another question concerning the behavioural simulation with ISE software.
How can I do to see the internal signals of the top level entity?
12-20-2011 03:57 AM