When I look at my CPLD Reports - Errors/Warnings I get the following:
[Warning]:INFO:Cpld - Inferring BUFG constraint for signal 'clock_osc' based upon the LOC constraint 'P38'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored.
I am not sure what this means? Can anyone explain?