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Observer yinyadong
Observer
1,481 Views
Registered: ‎06-06-2017

Can vivado be more unstable?

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Hi Guys,

 

Just look at this diagram!

I use vivado 2018.2 to capture some signals in my project. There is no error, no warning about ILA core when synthesis, implement and program. BUT! The ILA always be Idle status!!!  IDLE!!!! IDLE!!!!!!! no mater what I do it just stays IDE!!!! IDLE, Yes, IDLE!. I re do the project again. It still stays IDLE! All my day is fighting with VIVADO, trying to make ILA works. How lazy it is! It refused working for me.

 

This is intolerable!!!   intolerable!!!   intolerable!!!   intolerable!!!  It is not for the First time!!! Holy **bleep**!

 

 

 

VIVADO_is_shit.png
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1 Solution

Accepted Solutions
Scholar brimdavis
Scholar
1,434 Views
Registered: ‎04-26-2012

Re: Can vivado be more unstable?

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@yinyadong  "This is fixed by lower the download speed."

 

The Xilinx ILA cores require that the ILA input clock be faster than the JTAG clock.

 

If this is not the case, the ILA triggering/capture/status for all ILA's can behave erratically.

 

I can't find the documentation/Answer Record that describes this issue at the moment; as I recall the requirement is that the slowest ILA clock must be  2x (or maybe 4x)  faster than the JTAG clock.

 

EDIT: found the JTAG clock info in UG908 :

JTAG_clk.png

 

 

-Brian

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8 Replies
Scholar dpaul24
Scholar
1,455 Views
Registered: ‎08-07-2014

Re: Can vivado be more unstable?

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@yinyadong,

 

from the pic, I don't see any 'Trigger Setup' defined.

You have to define a trigger, after which ILA will capture some data for you and changel its IDLE state.

 

This thread might help you to understand ILA better:

https://forums.xilinx.com/t5/Design-Tools-Others/How-to-successfully-trigger-an-ILA-core-in-Vivado/td-p/782397

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Observer yinyadong
Observer
1,447 Views
Registered: ‎06-06-2017

Re: Can vivado be more unstable?

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 Hi Dpau

I tried what I can with Trigger Setup, nothing works.

 

thanks 

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Highlighted
Explorer
Explorer
1,410 Views
Registered: ‎10-05-2010

Re: Can vivado be more unstable?

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Something to try:

 

1. Close the project

 

2. In the directory <projectname>.hw, there is a directory hw_1. Rename this directory and then open the project in Vivado again.

 

3. Vivado will make a new hw_1 directory.

 

4. Try using chipscope again.

 

Vivado keeps waveform data around from run to run, and sometimes things just don't match.

 

---

Joe Samson

 

Tags (1)
Moderator
Moderator
1,394 Views
Registered: ‎02-09-2017

Re: Can vivado be more unstable?

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I agree with @josephsamson suggestion.

 

You can also just delete everything in the <projectname>.hw folder and try again. 

 

That folder contain ILA related configuration, data, and waveform files. Sometimes it might get stuck with older files and not work correctly.

Andre Guerrero

Product Applications Engineer

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Observer yinyadong
Observer
1,378 Views
Registered: ‎06-06-2017

Re: Can vivado be more unstable?

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hi Joe,
I have spend almost one day tried all the ways you said, none works. Is there any other suggestion?
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Observer yinyadong
Observer
1,378 Views
Registered: ‎06-06-2017

Re: Can vivado be more unstable?

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I tried. But all the ways do not work.
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Observer yinyadong
Observer
1,348 Views
Registered: ‎06-06-2017

Re: Can vivado be more unstable?

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Hi I have found the reason.

 

The FPGA board I use is VCU118, which provide a USB port for program and debug. This issue is caused by download speed. when debug little signal it is OK, but when debug hundreds of signals, this issue occur. This is fixed by lower the download speed.

 

Regards,

Scholar brimdavis
Scholar
1,435 Views
Registered: ‎04-26-2012

Re: Can vivado be more unstable?

Jump to solution

@yinyadong  "This is fixed by lower the download speed."

 

The Xilinx ILA cores require that the ILA input clock be faster than the JTAG clock.

 

If this is not the case, the ILA triggering/capture/status for all ILA's can behave erratically.

 

I can't find the documentation/Answer Record that describes this issue at the moment; as I recall the requirement is that the slowest ILA clock must be  2x (or maybe 4x)  faster than the JTAG clock.

 

EDIT: found the JTAG clock info in UG908 :

JTAG_clk.png

 

 

-Brian

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