Cannot see Debug cores

[astei87]

Hello Guys,

i have a problem with debugging in Vivado. Normaly it works always, but in

the current project not. I have set like always my debug signals with "setup De Bug". 

After generating the bitstream, i open the hardware manager, flash the device but i don't see any

debug signals. I receive the following message:

When i open the implemented design, i see that the debug cores are placed in the device. I Also see the 

Schemetic:

The Clock for the debug cores comes from the Processing System -> FCLK_CLK0. So it should be a free-running clock. 

Does anyone know what i did wrong? thanks

[balkris · Accepted solution]

your project may got corrupted. I think you can try with new project

https://forums.xilinx.com/t5/Design-Tools-Others/ILA-core-not-recognized-by-hardware-manager/td-p/552554

https://forums.xilinx.com/t5/Design-Tools-Others/Hardware-Manager-finds-no-debug-cores/td-p/710113

https://forums.xilinx.com/t5/Debug-Tools/Hardware-Manager-error-relative-ila-ip-core-vivado-13-4/td-p/396319

check this guide as well

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug908-vivado-programming-debugging.pdf

[arpansur]

Hi @astei87,

Can you please try connecting system clock to ILA and implement the design again?

Let us know if the issue persists after connecting sys_clk.

[astei87]

Thx for you help guys,

it seems that my design was somehow corrupted. I've built a new design and it works now. Thank you